PhiClock Generator. 9FGV1005C Datasheet

9FGV1005C Generator. Datasheet pdf. Equivalent

Part 9FGV1005C
Description Low-Power Programmable PhiClock Generator
Feature Low Phase-Noise, Low-Power Programmable PhiClock™ Generator 9FGV1005C Datasheet Description The 9F.
Manufacture Renesas
Datasheet
Download 9FGV1005C Datasheet



9FGV1005C
Low Phase-Noise, Low-Power
Programmable PhiClock™
Generator
9FGV1005C
Datasheet
Description
The 9FGV1005C is a member of the Renesas PhiClock™
programmable clock generator family. The 9FGV1005C provides
two copies of a single non-spread spectrum output frequency and
one copy of the crystal reference input. Two select pins allow for
hardware selection of the desired configuration, or two I2C bits
allow easy software selection of the desired configuration. The
user may configure any one of the four OTP configurations as the
default when operating in I2C mode. Four unique I2C addresses
are available, allowing easy I2C access to multiple components.
Typical Applications
HPC
Storage
10G/25G Ethernet
Fiber Optic Modules
SSDs
NVLink
Output Features
1 integer output frequency per configuration
2 programmable output pairs plus 1 LVCMOS REF output
1MHz–325MHz LVDS or LP-HCSL outputs
1MHz–200MHz LVCMOS outputs
Block Diagram
Features
1.8V–3.3V operation
Individual 1.8V–3.3V VDDO for each programmable output pair
Supports HCSL, LVDS and LVCMOS I/O standards
Supports LVPECL and CML logic with easy AC coupling – see
application note AN-891 for alternate terminations
HCSL utilizes Renesas' LP-HCSL technology for improved
performance, lower power and higher integration:
• Programmable output impedance of 85or 100
On-board OTP supports up to 4 complete configurations
Configuration selected via strapping pins or I2C
< 100mW at 1.8V, < 200mW at 3.3V (LP-HCSL outputs running
at 100MHz)
4 programmable I2C addresses: D0/D1, D2/D3, D4/D5, D6/D7
read/write
Supported by Renesas Timing Commander™ software
3 × 3 mm 16-LGA with integrated crystal option
(9FGV1005CQ)
Key Specifications
259fs rms typical phase jitter outputs at 156.25MHz (12kHz–
20MHz)
PCIe Gen1–5 compliant
PCIe Clocking Architectures
Common Clocked (CC)
Independent Reference without spread spectrum (SRnS)
Crystal is integrated
on 9FGV1005CQ
XIN/CLKIN
XO
VDDDp OTP_VPP VDDAp
OSC
REF0
VDDREFp
INT INT
PLL DIV
vSEL_I2C#
^SEL0/SCL
^SE L1/SDA
SMBus
Engine
Factory
Configuration
OUT1#
OUT1
VDDO1
OUT0#
OUT0
VDDO0
Control Logic
Internal terminations are available when LP-HCSL output format is selected.
EPAD/GND
©2020 Renesas Electronics Corporation
1
February 14, 2020



9FGV1005C
Pin Assignments
Figure 1. Pin Assignments for 3 × 3 mm 16-LGA Package – Top View
9FGV1005C Datasheet
XIN/CLKIN 1
XO 2
^SEL0/SCL 3
^SEL1/SDA 4
16 15 14 13
9FGV1005C
EPAD = GND
5678
12 OUT1
11 OUT1#
10 NC
9 VDDO0
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
NC 1
NC 2
^SEL0/SCL 3
^SEL1/SDA 4
16 15 14 13
9FGV1005CQ
EPAD = GND
5678
12 OUT1
11 OUT1#
10 NC
9 VDDO0
16-LGA 3 x 3 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
©2020 Renesas Electronics Corporation
2
February 14, 2020





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)