AD9500

a FEATURES 10 ps Delay Resolution 2.5 ns to 10 ␮ s Full-Scale Range Fully Differential Inputs Separate Trigger and Reset Inputs Low Power Dissipation—310 mW MIL-STD-883 Compliant Versions Available APPLICATIONS ATE Pulse Deskewing Arbitrary Waveform Generators High Stability Timing Source Multiple Phase Clock Generators TRIGGER TRIGGER RESET RESET Digitally Programmable Delay Generator AD9500 FUNCTIONAL BLOCK DIAGRAM CEXT +VS CS ECL COMMON AD9500 DIFFERENTIAL ANALOG INPUT STAGE ECL VOLTAGE REFERENCE TIMING CONTROL CIRCUIT Q Q INTERNAL DAC QR TTL LATCHES ECLREF RS REFERENCE CURRENT RSET –VS GROUND D0 D1 D2 D3 D4 D5 D6 D7 (LSB) (MSB) LATCH OFFSET ENABLE ADJUST GENERAL DESCRIPTION –VS The AD9500 is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500 is constructed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits. The AD9500 employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500 output is a complementary ECL stage, which also provides a Q R parallel output circuit to facilitate reset timing implementations. The digital control data is passed to the AD9500 through a transparen...