9FGL639

DATASHEET 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 9FGL639 XIN/CLKIN_25 X2_25 OSC PROGRAMMABLE SPREAD PLL STOP LOGIC 6 DIF(5:0) SDATA SCLK CONTROL LOGIC IDT® 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 1 9FGL639 REV A 061312 9FGL639 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 VDD GND NC VDD GND XIN/CLKIN_25 X2_25 NC VDD NC GND GND DIF_0 DIF_0# VDD DIF_5 DIF_5# DIF_4 DIF_4# DIF_2 DIF_2# DIF_3# DIF_3 IDT® 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 2 9FGL639 REV A 061312 9FGL639 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 IDT® 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 3 9FGL639 REV A 061312 9FGL639 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 IDT (Slave/Receiver) ACK ACK ACK ACK O O O ACK IDT (Slave/Receiver) ACK ACK ACK Data Byte Count=X Beginning Byte N O O O Byte N + X - 1 IDT® 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 4 9FGL639 REV A 061312 9FGL639 6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3 SMBus Table: Device Control Register, READ/WRITE ADDRESS (D2/D3) Byte 0 Pin # Name Control Function Type Bit 7 - Reserved Bit 6 - Reserved Bit 5 Spread Enable RW Bit 4 - Reserved Bit 3 - Reserved Bit 2 - Reserved Bit 1 - P Bit 0 - Reserved SMBus Table: Output Enable Register Byte 1 Pin # Name B...