Document
NOT RECOMMENDED FOR NEW DESIGNS INTERSIL SUGGESTS THE ISL22316 OR ISL22319
X9428 Low Noise/Low Power/2-Wire Bus
Single Digitally Controlled Potentiometer (XDCP™)
DATASHEET
FN8197 Rev 1.00 April 26, 2006
FEATURES
• Solid state potentiometer • 2-wire serial interface • Register oriented format
—Direct Read/Write/Transfer wiper position —Store as many as four positions per
potentiometer • Power supplies
—VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V • Low power CMOS —Standby current < 1µA —Ideal for battery operated applications • High reliability —Endurance–100,000 Data changes per bit per
register —Register data retention–100 years • 4-bytes of nonvolatile memory • 10k resistor array • Resolution: 64 taps each potentiometer • 16 Ld SOIC, 14 Ld TSSOP packages • Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9428 integrates a digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit.
The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC VSS
V+
V–
SCL SDA
A0 A2 A3
WP
Interface and
Control Circuitry
8 Data
R0 R1 R2 R3
Wiper Counter Register (WCR)
VH/RH
VL/RL VW/RW
FN8197 Rev 1.00 April 26, 2006
Page 1 of 21
X9428 Low Noise/Low Power/2-Wire Bus
Ordering Information
PART NUMBER
PART MARKING
X9428WS16*
X9428WS
X9428WS16Z* (Note) X9428WS Z
X9428WS16I*
X9428WS I
X9428WS16IZ* (Note) X9428WS ZI
X9428WV14*
X9428 W
X9428WV14Z* (Note) X9428 Z
X9428WV14I*
X9428 WI
X9428WV14IZ* (Note) X9428 ZI
X9428YS16* X9428YS16Z* (Note)
X9428YS X9428YS Z
X9428YS16I*
X9428YS I
X9428YS16IZ* (Note) X9428YS ZI
X9428YV14*
X9428 Y
X9428YV14Z* (Note) X9428 YZ
X9428YV14I*
X9428 YI
X9428YV14IZ* (Note) X9428 YZI
X9428WS16-2.7*
X9428WS16Z-2.7* (Note)
X9428WS16I-2.7*
X9428WS16IZ-2.7* (Note)
X9428WV14-2.7*
X9428WS F X9428WS ZF
X9428WS G X9428WS ZG
X9428 WF
X9428WV14Z-2.7* (Note)
X9428WV14I-2.7*
X9428 ZF X9428 WG
X9428WV14IZ-2.7* (Note)
X9428YS16-2.7*
X9428YS16Z-2.7* (Note)
X9428 ZG
X9428YS F X9428YS ZF
VCC LIMITS (V) 5 to ±10%
2.7 to 5.5
POTENTIOMETER ORGANIZATION (k)
10
2
10
2
TEMP. RANGE (°C)
0 to +70 0 to +70
-40 to +85 -40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70 0 to +70
-40 to +85 -40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70 0 to +70
-40 to +85 -40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70 0 to +70
PACKAGE
PKG. DWG. #
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
14 Ld TSSOP (4.4mm)
M14.173
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
16 Ld SOIC (300 mil) M16.3
16 Ld SOIC (300 mil) M16.3 (Pb-free)
FN8197 Rev 1.00 April 26, 2006
Page 2 of 21
X9428 Low Noise/Low Power/2-Wire Bus
Ordering Information (Continued)
PART NUMBER X9428YS16I-2.7*
PART MARKING
X9428YS G
VCC LIMITS (V) 2.7 to 5.5
POTENTIOMETER ORGANIZATION (k)
2
TEMP. RANGE (°C)
-40 to +85
PACKAGE
PKG. DWG. #
16 Ld SOIC (300 mil) M16.3
X9428YS16IZ-2.7* (Note)
X9428YS ZG
-40 to +85
16 Ld SOIC (300 mil) M16.3 (Pb-free)
X9428YV14-2.7*
X9428 YF
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9428YV14Z-2.7* (Note)
X9428 YZF
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
X9428YV14I-2.7*
X9428 YG
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
X9428YV14IZ-2.7* (Note)
X9428 YZG
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-free)
M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination fini.