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ICSSSTVF16857 Dataheets PDF



Part Number ICSSSTVF16857
Manufacturers Renesas
Logo Renesas
Description DDR 14-Bit Registered Buffer
Datasheet ICSSSTVF16857 DatasheetICSSSTVF16857 Datasheet (PDF)

�ENESAS ICSSSTVF16857 Advance Information DDR 14-Bit Registered Buffer Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation - Voo = 2.3V to2.7V • 48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H .

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�ENESAS ICSSSTVF16857 Advance Information DDR 14-Bit Registered Buffer Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signal • Meets SSTL_2 signal data • Supports SSTL_2 class I & II specifications • Low-voltage operation - Voo = 2.3V to2.7V • 48 pin TSS OP and TVS OP package Truth Table1 Inputs RESET# CLK CLK# L Xor Xor Floating Floating H t J, H t J, H LorH LorH D Xor Floating H L X Q Outputs Q L H L QlZ> Pin Configuration Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VDD QJ 5 44 DJ Q4 6 43 D4 Q5 7 42 D5 ->cc:ooGND VDDQ 8 9 t-- It) 41 D6 40 D7 Q6 10 39 CU<# Q7 VDDQ 11 12 LL. 38 37 vCoU(o GND 13 36 GND !::?Q8 Q9 VOOQ GNO 14 15 16 17 eeeInn-n 35 VREF 34 RESET# 33 08 32 09 Q10 18 31 010 Q11 19 30 D11 Q12 20 29 D12 VOOQ 21 28 VOO GND 22 27 GND Q13 23 26 013 Q14 24 25 014 48-Pin TSSOP & TVSOP 6.10 mm. Body, 0.50 mm. pitch= TSSOP 4.40 mm. Body, 0.40 mm. pitch= TSSOP (TVSOP) Notes: 1. H = High Signal Level L= Low Signal Level t = Transition LOW-to-HIGH .J,, = Transition HIGH -to LOW X = Irrelevant 2. Output level before the indicated steady state input conditions were established. Block Diagram CU< CL.K# RESET# R CU< D1 VREF-+-..u.� �----+----+------1�D-1 --' Q1 To 13 Other Channels 0746-10/28/02 ADVANCE INFORMATION documents contain infonnation on products in the fonnative or design phase development Characteristic data and other specifications are design goals. JCS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. © 2019 Renesas Electronics Corporation ×ÝÍÍÍÌÊÚïêèëé ß¼ª¿²½» ײº±®³¿¬·±² Ù»²»®¿´ Ü»-½®·°¬·±² ̸» ïìó¾·¬ ×ÝÍÍÍÌÊÚïêèëé ·- ¿ «²·ª»®-¿´ ¾«- ¼®·ª»® ¼»-·¹²»¼ º±® îòíÊ ¬± îòéÊ ÊÜÜ ±°»®¿¬·±² ¿²¼ ÍÍÌÔÁî ×ñÑ ´»ª»´-ô »¨½»°¬ º±® ¬¸» ÔÊÝÓÑÍ ÎÛÍÛÌý ·²°«¬ò Ü¿¬¿ º´±© º®±³ Ü ¬± Ï ·- ½±²¬®±´´»¼ ¾§ ¬¸» ¼·ºº»®»²¬·¿´ ½´±½µ øÝÔÕñÝÔÕý÷ ¿²¼ ¿ ½±²¬®±´ -·¹²¿´ øÎÛÍÛÌý÷ò ̸» °±-·¬·ª» »¼¹» ±º ÝÔÕ ·- «-»¼ ¬± ¬®·¹¹»® ¬¸» ¼¿¬¿ º´±© ¿²¼ ÝÔÕý ·- «-»¼ ¬± ³¿·²¬¿·² -«ºº·½·»²¬ ²±·-» ³¿®¹·²- ©¸»®» ¿- ÎÛÍÛÌýô ¿² ÔÊÝÓÑÍ ¿-§²½¸®±²±«- -·¹²¿´ô ·- ·²¬»²¼»¼ º±® «-» ¿¬ ¬¸» ¬·³» ±º °±©»®ó«° ±²´§ò ×ÝÍÍÍÌÊÚïêèëé -«°°±®¬- ´±©ó°±©»® -¬¿²¼¾§ ±°»®¿¬·±²ò ß ´±¹·½ ´»ª»´ •Ô±©Œ¿¬ ÎÛÍÛÌý ¿--«®»- ¬¸¿¬ ¿´´ ·²¬»®²¿´ ®»¹·-¬»®- ¿²¼ ±«¬°«¬- øÏ÷ ¿®» ®»-»¬ ¬± ¬¸» ´±¹·½ •Ô±©Œ-¬¿¬»ô ¿²¼ ¿´´·²°«¬ ®»½»·ª»®-ô ¼¿¬¿ øÜ÷ ¿²¼ ½´±½µ øÝÔÕñÝÔÕý÷ ¿®» -©·¬½¸»¼ ±ººòд»¿-» ²±¬» ¬¸¿¬ ÎÛÍÛÌý ³«-¬ ¿´©¿§¾» -«°°±®¬»¼ ©·¬¸ ÔÊÝÓÑÍ ´»ª»´- ¿¬ ¿ ª¿´·¼ ´±¹·½ -¬¿¬» ¾»½¿«-» ÊÎÛÚ ³¿§ ²±¬ ¾» -¬¿¾´» ¼«®·²¹ °±©»®ó«°ò ̱ »²-«®» ¬¸¿¬ ±«¬°«¬- ¿®» ¿¬ ¿ ¼»º·²»¼ ´±¹·½ -¬¿¬» ¾»º±®» ¿ -¬¿¾´» ½´±½µ ¸¿- ¾»»² -«°°´·»¼ô ÎÛÍÛÌý ³«-¬ ¾» ¸»´¼ ¿¬ ¿ ´±¹·½ •Ô±©Œ´»ª»´ ¼«®·²¹ °±©»® «°ò ײ ¬¸» ÜÜÎ Ü×ÓÓ ¿°°´·½¿¬·±²ô ÎÛÍÛÌý ·- -°»½·º·»¼ ¬± ¾» ½±³°´»¬»´§ ¿-§²½¸®±²±«- ©·¬¸ ®»-°»½¬ ¬± ÝÔÕ ¿²¼ ÝÔÕýò ̸»®»º±®»ô ²± ¬·³·²¹ ®»´¿¬·±²-¸·° ½¿² ¾» ¹«¿®¿²¬»»¼.


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