74FCT38075S

Low Skew 1 to 5 Clock Buffer 74FCT38075S DATASHEET Description The 74FCT38075S is a low skew, single input to five output, clock buffer. The 74FCT38075S has best in class additive phase Jitter of sub 50 fsec. IDT makes many non-PLL and PLL based low output skew devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Features Extremely low RMS Additive Phase Jitter: 50fs Low output skew: 50ps Packaged in 8-pin SOIC and 8-pin DFN Pb (lead) free package Low power CMOS technology Operating voltages of 1.8V to 3.3V Extended temperature range (-40°C to +105°C) Block Diagram ICLK Q0 Q1 Q2 Q3 Q4 74FCT38075S REVISION A 03/18/15 1 ©2015 Integrated Device Technology, Inc. 74FCT38075S DATASHEET Pin Assignments Q4 VDD ICLK GND 1 2 3 4 8 Q3 7 Q2 6 Q1 5 Q0 8-pin SOIC Q4 VDD ICLK GND 1 2 3 4 8 Q3 7 Q2 6 Q1 5 Q0 8-pin DFN Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name Q4 VDD ICLK GND Q0 Q1 Q2 Q3 Pin Type Output Power Input Power Output Output Output Output Pin Description Clock Output 4. Connect to +1.8V, +2.5 V, or +3.3 V. Clock input. Connect to ground. Clock output 0. Clock output 1. Clock Output 2. Clock Output 3. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be connected between VDD on pin 2 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock outp...