9DBV0441

4-Output 1.8V PCIe Gen1–4 ZDB/FOB with Zo = 100ohm 9DBV0441 DATASHEET Description The 9DBV0441 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100 for direct connection to 100 transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses. Typical Applications 1.8V PCIe Gen1–3 Zero Delay Buffer (ZDB) 1.8V PCIe Gen1–4 Fanout Buffer (FOB) Output Features Four 1–200Hz Low-Power (LP) HCSL DIF pairs with ZO = 100 Key Specifications DIF cycle-to-cycle jitter < 50ps DIF output-to-output skew < 50ps DIF additive phase jitter is < 100fs rms for PCIe Gen4 DIF additive phase jitter < 300fs rms for 12kHz-20MHz Block Diagram Features/Benefits Direct connection to 100 transmission lines; saves 16 resistors compared to standard HCSL outputs 53mW typical power consumption in PLL mode; minimal power consumption Spread Spectrum (SS) compatible; allows use of SS for EMI reduction OE# pins; support DIF power management HCSL compatible differential input; can be driven by common clock sources Programmable Slew rate for each output; allows tuning for various line lengths Programmable output amplitude; allows tuning for various application environments Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application Outputs blocked until PLL is locked; clean system start-up Software selectable 50MHz or 125M...