IDT5T30553

LOW SKEW 1 TO 4 CLOCK BUFFER DATASHEET IDT5T30553 Description The IDT5T30553 is a low skew, single input to four output, clock buffer. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Features Extremely low skew outputs (50 ps maximum) Packaged in 8-pin SOIC – Pb-free, RoHS compliant Low power CMOS technology Operating voltages of 2.5 V to 3.3 V Output Enable pin tri-states outputs Commercial (0 to +70°C) and Industrial (-40°C to +85°C) temperature ranges Block Diagram ICLK Q0 Q1 Q2 Q3 Output Enable IDT® LOW SKEW 1 TO 4 CLOCK BUFFER 1 IDT5T30553 REV F 121013 IDT5T30553 LOW SKEW 1 TO 4 CLOCK BUFFER Pin Assignment VDD Q0 Q1 GND 1 2 3 4 8 OE 7 Q3 6 Q2 5 ICLK 8-pin SOIC FAN OUT BUFFER Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name VDD Q0 Q1 GND ICLK Q2 Q3 OE Pin Type Power Output Output Power Input Output Output Input Pin Description Connect to +2.5 V or +3.3 V. Clock output 0. Clock output 1. Connect to ground. Clock input. Clock Output 2. Clock Output 3. Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33  series terminating resistor may be used on each clock output if the trace ...