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ICS672-02 Dataheets PDF



Part Number ICS672-02
Manufacturers Renesas
Logo Renesas
Description QUADRACLOCK QUADRATURE DELAY BUFFER
Datasheet ICS672-02 DatasheetICS672-02 Datasheet (PDF)

QUADRACLOCK QUADRATURE DELAY BUFFER DATASHEET ICS672-01/02 Description The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or lat.

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QUADRACLOCK QUADRATURE DELAY BUFFER DATASHEET ICS672-01/02 Description The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT’s proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The ICS672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin. IDT manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world. Block Diagram Features • Packaged in 16-pin SOIC • Pb (lead) free package, RoHS compliant • Input clock range from 5 MHz to 150 MHz (depends on multiplier) • Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02) • Zero input-output delay • Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections • Four accurate (<250 ps) outputs with 0°, 90°, 180°, and 270° phase shift from ICLK, and one FBCLK (0°) • Separate supply for output clocks from 2.5 V to 5 V • Full CMOS outputs (TTL compatible) • Tri-state mode for board-level testing • Includes Power-down for power savings • Advanced, low power, sub-micron CMOS process • 3.3 V to 5 V operating voltage • Industrial temperature version available IN FBIN S2:S0 3 VDD 2 GND 3 VDDIO PLL Multiplier and Quadrature Generation Control Logic Power Down plus Tri-state CLK0 CLK90 CLK180 CLK270 CLKFB External Feedback IDT™ / ICS™ QUADRACLOCK QUADRATURE DELAY BUFFER 1 ICS672-01/02 REV L 051310 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER Pin Assignment ICLK CLK90 CLK180 CLK270 VDDIO GND GND S0 1 2 3 4 5 6 7 8 16 FBIN 15 FBCLK 14 CLK0 13 VDD 12 GND 11 VDD 10 S2 9 S1 ZERO DELAY BUFFER Output Clock Mode Select Table S2 S1 S0 000 001 010 011 100 101 110 111 Output Clocks Power-down + tri-state x1 x2 x3 x4 x5 x6 x0.5 Pin Descriptions Pin Number 1 2 3 4 5 6, 7, 12 8 9 10 11, 13 14 15 16 Pin Name ICLK CLK90 CLK180 CLK270 VDDIO GND S0 S1 S2 VDD CLK0 FBCLK FBIN Pin Type Pin Description Input Clock input. Output Clock output (90° delayed from CLK0). Output Clock output (180° delayed from CLK0). Output Clock output (270° delayed from CLK0). Power Supply voltage for input and output clocks. Must not exceed VDD. Power Connect to ground. Input Select input 0. See table above. Input Select input 1. See table above. Input Select input 2. See table above. Power Connect to 3.3 V or 5.0 V. Output Clock output phase aligned to ICLK. Output Feedback clock output (0° phase shift from CLK0). Input Feedback clock input. in normal operation, connect to FBCLK. IDT™ / ICS™ QUADRACLOCK QUADRATURE DELAY BUFFER 2 ICS672-01/02 REV L 051310 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER External Components The ICS672-01/02 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 11 and 12, and VDD and GND on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series termination resistor of 33Ω may be used close to each clock output pin to reduce reflections. Operation and Applications The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock (ICLK). Phase shifts of 0° (CLK0), 90° (CLK90), 180° (CLK180), and 270° (CLK270) are provided, plus one feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by the table on page 2. Refer to the illustrations in Figure 1 and Figure 2. FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02. FBCLK has a 0° phase shift from ICLK. ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 1. Phase alignment of input and output clocks (x1 multiplier) ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 2. Phase alignment of input and output clocks (x2 multiplier) IDT™ / ICS™ QUADRACLOCK QUADRATURE DELAY BUFFER 3 ICS672-01/02 REV L 051310 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS672-01/02. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating .


ICS672-01 ICS672-02 ICS673-01


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