70T651-9S

HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE 70T651/9S Features ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 10/12ns (max.) ◆ RapidWrite Mode simplifies high-speed consecutive write cycles ◆ Dual chip enables allow for depth expansion without external logic ◆ IDT70T651/9 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flags Functional Block Diagram BE 3L ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ Fully asynchronous operation from either port ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ Sleep Mode Inputs on both ports ◆ Supports JTAG features compliant to IEEE 1149.1 ◆ Single 2.5V (±100mV) power supply for core ◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port ◆ Available in a 256-ball Ball Grid Array and 208-ball fine pitch Ball Grid Array ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Green parts available, see ordering information BE3R BE2L BE2R BE1L BE0L BE 1R BE0R R/WL CE0L CE1L BB BB B BBB EE EE E EEE 01 23 3 210 L L L L RRRR R/WR CE0R CE1R OEL I/O0L- ...