Termination Regulator. TPS51200 Datasheet

TPS51200 Regulator. Datasheet pdf. Equivalent

Part TPS51200
Description Sink and Source DDR Termination Regulator
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TPS51200
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TPS51200
SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020
TPS51200 Sink and Source DDR Termination Regulator
1 Features
1 Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
• VLDOIN Voltage Range: 1.1 V to 3.5 V
• Sink and Source Termination Regulator Includes
Droop Compensation
• Requires Minimum Output Capacitance of 20-μF
(Typically 3 × 10-μF MLCCs) for Memory
Termination Applications (DDR)
• PGOOD to Monitor Output Regulation
• EN Input
• REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider
• Remote Sensing (VOSNS)
• ±10-mA Buffered Reference (REFOUT)
• Built-in Soft Start, UVLO, and OCL
• Thermal Shutdown
• Supports DDR, DDR2, DDR3, DDR3L, Low-
Power DDR3, and DDR4 VTT Applications
• 10-Pin VSON Package With Thermal Pad
2 Applications
• Memory Termination Regulator for DDR, DDR2,
DDR3, DDR3L, Low-Power DDR3 and DDR4
• Notebooks, Desktops, and Servers
• Telecom and Datacom
• Base Stations
• LCD-TVs and PDP-TVs
• Copiers and Printers
• Set-Top Boxes
3 Description
The TPS51200 device is a sink and source double
data rate (DDR) termination regulator specifically
designed for low input voltage, low-cost, low-noise
systems where space is a key consideration.
The TPS51200 maintains a fast transient response
and requires a minimum output capacitance of only
20 μF. The TPS51200 supports a remote sensing
function and all power requirements for DDR, DDR2,
DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT
bus termination.
In addition, the TPS51200 provides an open-drain
PGOOD signal to monitor the output regulation and
an EN signal that can be used to discharge VTT
during S3 (suspend to RAM) for DDR applications.
The TPS51200 is available in the thermally efficient
10-pin VSON thermal pad package, and is rated both
Green and Pb-free. It is specified from –40°C to
+85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS51200
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified DDR Application
VDDQ
VLDOIN
VTT
1 REFIN
VIN 10
TPS51200
2 VLDOIN PGOOD 9
3 VO
GND 8
4 PGND
EN 7
5 VOSNS REFOUT 6
3.3 VIN
PGOOD
SLP_S3
VTTREF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



TPS51200
TPS51200
SLUS812D – FEBRUARY 2008 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics .............................................. 8
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
8 Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
8.3 System Examples ................................................... 21
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
10.3 Thermal Design Considerations............................ 28
11 Device and Documentation Support ................. 30
11.1 Device Support...................................................... 30
11.2 Documentation Support ....................................... 30
11.3 Community Resources.......................................... 30
11.4 Trademarks ........................................................... 30
11.5 Electrostatic Discharge Caution ............................ 30
11.6 Glossary ................................................................ 30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2016) to Revision D
Page
• Added "keep total REFOUT capacitance below 0.47 μF" in Pin Functions table ................................................................. 4
Changes from Revision B (September 2016) to Revision C
Page
• Added references to DDR3L DRAM technology throughout .................................................................................................. 1
• Added DDR3L test conditions to Output DC voltage, VO and REFOUT specification .......................................................... 6
• Added Figure 4 ....................................................................................................................................................................... 8
• Added Figure 9 ....................................................................................................................................................................... 9
• Updated Figure 16 to include DDR3L data .......................................................................................................................... 10
Changes from Revision A (September 2015) to Revision B
Page
• Changed " –10 mA < IREFOUT < 10 mA" to "–1 mA < IREFOUT < 1 mA" in all test conditions for the REFOUT voltage
tolerance to VREFIN specification ............................................................................................................................................. 7
• Changed all MIN and MAX values from "15" to "12" for all test conditions for the REFOUT voltage tolerance to
VREFIN specification ................................................................................................................................................................. 7
• Updated Figure 19 ............................................................................................................................................................... 12
• Added REFOUT (VREF) Consideration for DDR2 Applications section................................................................................. 16
• Updated Figure 28 and Table 3............................................................................................................................................ 21
• Added clarity to Layout Guidelines section. ......................................................................................................................... 27
Changes from Original (February 2008) to Revision A
Page
• Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1
• Changed “PowerPAD” references to “thermal pad” throughout ............................................................................................. 4
2
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