Termination Regulator. TPS51200-Q1 Datasheet

TPS51200-Q1 Regulator. Datasheet pdf. Equivalent

TPS51200-Q1 Datasheet
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Part TPS51200-Q1
Description Sink and Source DDR Termination Regulator
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Texas Instruments TPS51200-Q1
Product
Folder
Order
Now
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
TPS51200-Q1
SLUS984C – NOVEMBER 2009 – REVISED APRIL 2018
TPS51200-Q1 Sink and Source DDR Termination Regulator
1 Features
1 Qualified for Automotive Applications
• AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
• Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
• VLDOIN Voltage Range: 1.1 V to 3.5 V
• Sink/Source Termination Regulator Includes
Droop Compensation
• Requires Minimum Output Capacitance of 20-μF
(typically 3 × 10-μF MLCCs) for Memory
Termination Applications (DDR)
• PGOOD to Monitor Output Regulation
• EN Input
• REFIN Input Allows for Flexible Input Tracking
Either Directly or Through Resistor Divider
• Remote Sensing (VOSNS)
• ±10-mA Buffered Reference (REFOUT)
• Built-in Soft Start, UVLO and OCL
• Thermal Shutdown
• Meets DDR, DDR2 JEDEC Specifications;
Supports DDR3, DDR3L, Low-Power DDR3 and
DDR4 VTT Applications
• VSON-10 Package With Exposed Thermal Pad
2 Applications
• Memory Termination Regulator for DDR, DDR2,
DDR3, DDR3L, Low Power DDR3 and DDR4
• Notebook, Desktop, Server
• Telecom and Datacom, GSM Base Station, LCD-
TV and PDP-TV, Copier and Printer, Set-Top Box
3 Description
The TPS51200-Q1 device is a sink and source
double-data-rate (DDR) termination regulator
specifically designed for low input voltage, low-cost,
low-noise systems where space is a key
consideration.
The TPS51200-Q1 device maintains a fast transient
response and only requires a minimum output
capacitance of 20 μF. The TPS51200-Q1 device
supports a remote sensing function and all power
requirements for DDR, DDR2, DDR3, DDR3L, Low
Power DDR3 and DDR4 VTT bus termination.
In addition, the TPS51200-Q1 device provides an
open-drain PGOOD signal to monitor the output
regulation and an EN signal that can be used to
discharge VTT during S3 (suspend to RAM) for DDR
applications.
The TPS51200-Q1 device is available in the
thermally-efficient VSON-10 package, and is rated
both green and Pb-free. The device is specified from
–40°C to 125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS51200-Q1
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Standard DDR Application
VDDQ
TPS51200-Q1
1 REFIN
VIN 10
3.3 VIN
VLDOIN
VTT
2 VLDOIN PGOOD 9
3 VO
GND 8
4 PGND
EN 7
5 VOSNS REFOUT 6
PGOOD
SLP_S3
VTTREF
0.1 µF
UDG-08025
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



Texas Instruments TPS51200-Q1
TPS51200-Q1
SLUS984C – NOVEMBER 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics .......................................... 6
6.7 Typical Characteristics .............................................. 7
7 Detailed Description ............................................ 10
7.1 Overview ................................................................ 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 26
10.3 Thermal Considerations ........................................ 27
11 Device and Documentation Support ................. 29
11.1 Device Support...................................................... 29
11.2 Documentation Support ........................................ 29
11.3 Receiving Notification of Documentation Updates 29
11.4 Community Resource............................................ 29
11.5 Trademarks ........................................................... 29
11.6 Electrostatic Discharge Caution ............................ 29
11.7 Glossary ................................................................ 29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2015) to Revision C
Page
• Changed pinout diagram for compatibility with HTML versioin of the data sheet .................................................................. 3
• Added REFOUT specification for –1 mA IREFOUT 1 mA, condition ................................................................................... 5
• Corrected Typical Characteristics condition statement .......................................................................................................... 7
• Added Figure 4 ....................................................................................................................................................................... 7
• Added Figure 9 ....................................................................................................................................................................... 8
• Added Receiving Notification of Documentation Updates sectiion....................................................................................... 29
Changes from Revision A (April 2012) to Revision B
Page
• Added AEC-Q100 test guidance results for temperature grade and HBM and CDM classifications to Features list ............ 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
• Replaced references to PowerPAD with thermal pad ............................................................................................................ 1
• Deleted ORDERING INFORMATION table............................................................................................................................ 3
• Deleted DISSIPATION RATINGS TABLE .............................................................................................................................. 4
• Changed the thermal metric parameters in the Thermal Information table ........................................................................... 4
• Changed the test conditions for REFOUT source and sink current limits in the Electrical Characteristics table ................. 5
• Added -Q1 to device name throughout text of document..................................................................................................... 24
Changes from Original (November 2009) to Revision A
Page
• Added thermal table information for DRC package................................................................................................................ 4
2
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Product Folder Links: TPS51200-Q1



Texas Instruments TPS51200-Q1
www.ti.com
5 Pin Configuration and Functions
TPS51200-Q1
SLUS984C – NOVEMBER 2009 – REVISED APRIL 2018
DRC Package
10-Pin VSON With Exposed Thermal Pad
Top View
REFIN
VLDOIN
VO
PGND
VOSNS
1
10
2
9
3
Thermal
8
Pad
4
7
5
6
VIN
PGOOD
GND
EN
REFOUT
Not to scale
Pin Functions
PIN
I/O
NAME
NO.
DESCRIPTION
EN
7
I
For DDR VTT application, connect EN to SLP_S3. For any other applications, use EN as the ON/OFF
function. Keep EN voltage equal or lower than VIN voltage at all times.
GND
PGND (1)
8
— Ground. Signal ground. Connect to negative pin of the output capacitor.
4
— Power ground output for the LDO
PGOOD
9
O PGOOD output. Open drain pin. Indicates regulation.
REFIN
1
I Reference input
REFOUT
6
O
Reference output. Connect to GND through 0.1-μF ceramic capacitor. If there is REFOUT capacitor at DDR
side, keep the total capacitance on REFOUT pin below 1 μF. The REFOUT pin can not be open.
VIN
10
I
2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is
required.
VLDOIN
2
I Supply voltage for the LDO
VO
3
O Power output for the LDO. Minimum 20-μF capacitance is required. No maximum capacitance limit.
VOSNS
5
I Voltage sense output for the LDO. Connect to positive pin of the output capacitor or the load.
(1) Thermal pad connection. See Figure 34 in the Thermal Considerations section for additional information.
Copyright © 2009–2018, Texas Instruments Incorporated
Product Folder Links: TPS51200-Q1
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