BUCK CONTROLLER. TPS51163 Datasheet

TPS51163 CONTROLLER. Datasheet pdf. Equivalent

Part TPS51163
Description SYNCHRONOUS BUCK CONTROLLER
Feature TPS51113, TPS51163 www.ti.com .......................................................................
Manufacture etcTI
Datasheet
Download TPS51163 Datasheet



TPS51163
TPS51113, TPS51163
www.ti.com ....................................................................................................................................................................................................... SLUS864 – MAY 2009
SYNCHRONOUS BUCK CONTROLLER WITH HIGH-CURRENT GATE DRIVER
Check for Samples :TPS51113 TPS51163
FEATURES
1
• Flexible Power Rails: 5 V to 12 V
• Reference: 800 mV ± 0.8%
• Voltage Mode Control
• Support Pre-biased Startup
• Programmable Overcurrent Protection with
Low-Side RDS(on) Current Sensing
• Fixed 300-kHz (TPS51113) and 600-kHz
(TPS51163) Switching Frequency
• UV/OV Protections and Power Good Indicator
• Internal Soft-start
• Integrated High-Current Drivers Powered by
VDD
• 10-Pin 3 × 3 SON Package
APPLICATIONS
• Server and Desktop Computer Subsystem
Power Supplies (MCH, IOCH, PCI, Termination)
• Distributed Power Supplies
• General DC-DC Converters
DESCRIPTION
The TPS51113 and TPS51163 are cost-optimized,
feature rich, single-channel synchronous-buck
controllers that operates from a single 4.5-V to 13.2-V
supply and can convert an input voltage as low as
1.5 V.
The controller implements voltage mode control with
a fixed 300-kHz (TPS51113) and 600-kHz
(TPS51163) switching frequency. The overcurrent
(OC) protection employs the low-side RDS(on) current
sensing and has user-programmable threshold. The
OC threshold is set by the resistor from LDRV_OC
pin to GND. The resistor value is read when the
over-current programming circuit applies 10 μA of
current to the LDRV_OC pin during the calibration
phase of the start-up sequence.
The TPS51113/TPS51163 also supports output
pre-biased startup.
The integrated gate driver is directly powered by
VDD. VDD can be connected to VIN in some
applications. The strong gate drivers with low
deadtime allow for the utilization of larger MOSFETs
to achieve higher efficiency. An adaptive anti-cross
conduction scheme is used to prevent shoot-through
between the power FETs.
TYPICAL APPLICATION CIRCUIT
+
VOUT
VDD
VIN
Q1
L1
Q2
C6 C7
D1
TPS51113\TPS51163
1 BOOT
C5
2 SW
PGOOD 10
VOS 9
3 HDRV
FB 8
4 LDRV_OC COMP_EN 7
ROC
5 GND
VDD 6
11
VOUT
R6
R4
R5
C4
R1
C2
C1
R2
Enable
C3
R3
RBIAS
UDG-08105
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated



TPS51163
TPS51113, TPS51163
SLUS864 – MAY 2009 ....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. ORDERING INFORMATION(1)
ORDERABLE
DEVICE
TPS51113DRCR
TPS51163DRCR
TPS51113DRCT
TPS51163DRCT
TYPE
SON
SON
DRAWING PINS QTY
DRC
10 3000
DRC
10 250
ECO PLAN
Green
(RoHS and no Sb/Br)
Green
(RoHS and no Sb/Br)
LEAD/BALL
FINISH
CU NiPDAU
CU NiPDAU
MSL PEAK
TEMPERATURE
Level-2-260C-1Year
Level-2-260C-1Year
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1) (2)
Over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.)
PARAMETER
VALUE
UNIT
VDD
–0.3 to 15
BOOT
–0.3 to 30
Input voltage range
BOOT, to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
–5.0 to 15
V
BOOT, (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
–5.0 to 37
All other pins
–0.3 to 3.6
SW
–0.3 to 22
SW, (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
–5.0 to 30
HDRV
–0.3 to 30
HDRV to SW (negative overshoot –5 V for t < 25 ns,
125 V × ns/t for 25 ns < t< 100 ns)
–5.0 to 15
Output voltage range HDRV (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
–5.0 to 37
V
LDRV_OC
–0.3 to 15
LDRV_OC (negative overshoot –5 V for t < 25ns,
125 V × ns/t for 25 ns < t < 100 ns)
–5.0 to 15
PGOOD
–0.3 to 15
All other pins
–0.3 to 3.6
TJ Operating junction temperature
Tstg Storage junction temperature
–40 to 125
°C
–55 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
Human Body Model (HBM)
Charged Device Model (CDM)
MIN TYP MAX UNIT
2500
V
1500
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS51113 TPS51163





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