Monostable Multivibrator. CD54HC221 Datasheet

CD54HC221 Multivibrator. Datasheet pdf. Equivalent

Part CD54HC221
Description Dual Monostable Multivibrator
Feature Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC2.
Manufacture etcTI
Datasheet
Download CD54HC221 Datasheet



CD54HC221
Data sheet acquired from Harris Semiconductor
SCHS166F
November 1997 - Revised October 2003
CD54HC221, CD74HC221,
CD74HCT221
High-Speed CMOS Logic
Dual Monostable Multivibrator with Reset
[ /Title
(CD74
HC221
,
CD74
HCT22
1)
/Sub-
ject
(High
Speed
CMOS
Logic
Dual
Monos
table
Multi-
Features
Description
• Overriding RESET Terminates Output Pulse
• Triggering from the Leading or Trailing Edge
• Q and Q Buffered Outputs
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on B Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD54HC221
(CERDIP)
CD74HC221
(PDIP, SOIC, SOP, TSSOP)
CD74HCT221
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1R 3
1Q 4
2Q 5
2CX 6
2CXRX 7
GND 8
16 VCC
15 1CXRX
14 1CX
13 1Q
12 2Q
11 2R
10 2B
9 2A
The ’HC221 and CD74HCT221 are dual monostable
multivibrators with reset. An external resistor (RX) and an
external capacitor (CX) control the timing and the accuracy
for the circuit. Adjustment of RX and CX provides a wide
range of output pulse widths from the Q and Q terminals.
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.
Once triggered, the outputs are independent of further trigger
inputs on A and B. The output pulse can be terminated by a
LOW level on the Reset (R) pin. Trailing Edge triggering (A)
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.
The minimum value of external resistance, RX, is typically 500.
The minimum value of external capacitance, CX, is 0pF. The
calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V.
Ordering Information
PART NUMBER TEMP. RANGE (oC)
PACKAGE
CD54HC221F3A
-55 to 125
16 Ld CERDIP
CD74HC221E
-55 to 125
16 Ld PDIP
CD74HC221M
-55 to 125
16 Ld SOIC
CD74HC221MT
-55 to 125
16 Ld SOIC
CD74HC221M96
-55 to 125
16 Ld SOIC
CD74HC221NSR
-55 to 125
16 Ld SOP
CD74HC221PW
-55 to 125
16 Ld TSSOP
CD74HC221PWR
-55 to 125
16 Ld TSSOP
CD74HC221PWT
-55 to 125
16 Ld TSSOP
CD74HCT221E
-55 to 125
16 Ld PDIP
CD74HCT221M
-55 to 125
16 Ld SOIC
CD74HCT221MT
-55 to 125
16 Ld SOIC
CD74HCT221M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



CD54HC221
CD54HC221, CD74HC221, CD74HCT221
Functional Diagram
1CX 1RX
14
15
VCC
1CX
1CXRX
13
1A
1Q
1
MONO 1
4
1B
1Q
2
1R
3
11
2R
9
2A
10
2B
MONO 2
5
2Q
12
2Q
2CX
6
2CXRX
7
2CX 2RX
VCC
TRUTH TABLE
INPUTS
A
B
R
H
X
H
X
L
H
L
H
OUTPUTS
Q
Q
L
H
L
H
H
H
X
X
L
L
H
L
H
(Note 3)
(Note 3)
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, = Transition from
Low to High Level, = Transition from High to Low Level,
= One High Level
Pulse,
= One Low Level Pulse
NOTE:
1. For this combination the reset input must be low and the following sequence
must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1
(or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low-
to-high and the device will be triggered.
2





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