Parity Generator/Checker. CD74HC280 Datasheet

CD74HC280 Generator/Checker. Datasheet pdf. Equivalent

Part CD74HC280
Description 9-Bit Odd/Even Parity Generator/Checker
Feature Data sheet acquired from Harris Semiconductor SCHS175D November 1997 - Revised October 2003 CD54HC2.
Manufacture etcTI
Datasheet
Download CD74HC280 Datasheet



CD74HC280
Data sheet acquired from Harris Semiconductor
SCHS175D
November 1997 - Revised October 2003
CD54HC280, CD74HC280,
CD54HCT280, CD74HCT280
High-Speed CMOS Logic
9-Bit Odd/Even Parity Generator/Checker
[ /Title
(CD74
HC280
,
CD74
HCT28
0)
/Sub-
ject
(High
Speed
CMOS
Logic
9-Bit
Odd/E
ven
Parity
Features
Description
Typical Propagation Delay
CL = 15pF, TA = 25oC
=
17ns
at
VCC
=
5V,
• Replaces LS180 Types
• Easily Cascadable
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator
checker devices. Both even and odd parity outputs are
available for checking or generating parity for words up to nine
bits long. Even parity is indicated (ΣE output is high) when an
even number of data inputs is high. Odd parity is indicated
(ΣO output is high) when an odd number of data inputs is
high. Parity checking for words larger than 9 bits can be
accomplished by tying the ΣE output to any input of an
additional HC/HCT280 parity checker.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC280F3A
-55 to 125 14 Ld CERDIP
CD54HCT280F3A
-55 to 125 14 Ld CERDIP
CD74HC280E
-55 to 125 14 Ld PDIP
CD74HC280MT
-55 to 125 14 Ld SOIC
CD74HC280M96
-55 to 125 14 Ld SOIC
CD74HCT280E
-55 to 125 14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC280, CD54HCT280
(CERDIP)
CD74HC280
(PDIP, SOIC)
CD74HCT280
(PDIP)
TOP VIEW
I6 1
I7 2
NC 3
I8 4
ΣE 5
ΣO 6
GND 7
14 VCC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Functional Diagram
8
I0
9
I1
10
I2
11
I3
12
I4
13
I5
1
I6
2
I7
4
I8
5
EVEN
6
ODD
GND = 7
VCC = 14
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



CD74HC280
CD54HC280, CD74HC280, CD54HCT280, CD74HCT280
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
86
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
SYMBOL
TEST
CONDITIONS
25oC
VI (V) IO (mA) VCC (V) MIN TYP MAX
VIH
-
-
VIL
-
-
VOH
VOL
II
ICC
VIH or
VIL
-0.02
-0.02
-0.02
-4
-5.2
VIH or
VIL
0.02
0.02
0.02
4
5.2
VCC or
-
GND
VCC or
0
GND
2
1.5 -
-
4.5 3.15 -
-
6
4.2 -
-
2
-
- 0.5
4.5
-
- 1.35
6
-
- 1.8
2
1.9 -
-
4.5 4.4 -
-
6
5.9 -
-
4.5 3.98 -
-
6
5.48 -
-
2
-
- 0.1
4.5
-
- 0.1
6
-
- 0.1
4.5
-
- 0.26
6
-
- 0.26
6
-
- ±0.1
6
-
-
8
-40oC TO 85oC
MIN MAX
1.5
-
3.15
-
4.2
-
-
0.5
-
1.35
-
1.8
1.9
-
4.4
-
5.9
-
3.84
-
5.34
-
-
0.1
-
0.1
-
0.1
-
0.33
-
0.33
-
±1
-
80
-55oC TO 125oC
MIN MAX UNITS
1.5
-
V
3.15
-
V
4.2
-
V
-
0.5
V
-
1.35
V
-
1.8
V
1.9
-
V
4.4
-
V
5.9
-
V
3.7
-
V
5.2
-
V
-
0.1
V
-
0.1
V
-
0.1
V
-
0.4
V
-
0.4
V
-
±1
µA
-
160
µA
2





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