Phase-Locked Loop. CD74HCT297 Datasheet

CD74HCT297 Loop. Datasheet pdf. Equivalent

Part CD74HCT297
Description Digital Phase-Locked Loop
Feature Data sheet acquired from Harris Semiconductor SCHS177B November 1997 - Revised May 2003 CD54HC297, .
Manufacture etcTI
Datasheet
Download CD74HCT297 Datasheet



CD74HCT297
Data sheet acquired from Harris Semiconductor
SCHS177B
November 1997 - Revised May 2003
CD54HC297, CD74HC297,
CD74HCT297
High-Speed CMOS Logic
Digital Phase-Locked Loop
[ /Title
(CD74
HC297
,
CD74
HCT29
7)
/Sub-
ject
(High-
Speed
CMOS
Logic
Digi-
tal
Phase-
Locked
Features
Description
• Digital Design Avoids Analog Compensation Errors
• Easily Cascadable for Higher Order Loops
• Useful Frequency Range
- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)
• Dynamically Variable Bandwidth
• Very Narrow Bandwidth Attainable
• Power-On Reset
• Output Capability
- Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/DOUT
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• ’HC297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V
- High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
• CD74HCT297 Types
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility
VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility II 1µA at VOL, VOH
Pinout
CD54HC297
(CERDIP)
CD74HC297, CD74HCT29
(PDIP)
TOP VIEW
B1
A2
ENCTR 3
KCP 4
I/DCP 5
D/U 6
I/DOUT 7
GND 8
16 VCC
15 C
14 D
13 φA2
12 ECPDOUT
11 XORPDOUT
10 φB
9 φA1
The ’HC297 and CD74HCT297 are high-speed silicon gate
CMOS devices that are pin-compatible with low power Schot-
tky TTL (LSTTL).
These devices are designed to provide a simple, cost-effec-
tive solution to high-accuracy, digital, phase-locked-loop appli-
cations. They contain all the necessary circuits, with the
exception of the divide-by-N counter, to build first-order
phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
have a 50% duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the build-
ing blocks external to the package, makes it easy for the
designer to incorporate ripple cancellation (see Figure 2) or to
cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally programmable
according to the K-counter function table. With A, B, C and D
all LOW, the K-counter is disabled. With A HIGH and B, C and
D LOW, the K-counter is only three stages long, which widens
the bandwidth or capture range and shortens the lock time of
the loop. When A, B, C and D are all programmed HIGH, the
K-counter becomes seventeen stages long, which narrows
the bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A to
D inputs can maximize the overall performance of the digital
phase-locked-loop.
The ’HC297 and CD74HCT297 can perform the classic first
order phase-locked-loop function without using analog com-
ponents. The accuracy of the digital phase-locked-loop
(DPLL) is not affected by VCC and temperature variations but
depends solely on accuracies of the K-clock and loop propa-
gation delays.
Ordering Information
PART NUMBER
CD54HC297F3A
CD74HC297E
CD74HCT297E
TEMP. RANGE (oC)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1



CD74HCT297
CD54HC297, CD74HC297, CD74HCT297
The phase detector generates an error signal waveform that,
at zero phase error, is a 50% duty factor square wave. At the
limits of linear operation, the phase detector output will be
either HIGH or LOW all of the time depending on the direction
of the phase error (φIN - φOUT). Within these limits the phase
detector output varies linearly with the input phase error
according to the gain Kd, which is expressed in terms of
phase detector output per cycle or phase error. The phase
detector output can be defined to vary between ±1 according
to the relation:
phase detector output = %------H----I--G-----H-1---0-----0-%------L---O-----W----
The output of the phase detector will be Kdφe, where the
phase error φe = φIN - φOUT.
EXCLUSIVE-OR phase detectors (XORPD) and edge-con-
trolled phase detectors (ECPD) are commonly used digital
types. The ECPD is more complex than the XORPD logic
function but can be described generally as a circuit that
changes states on one of the transitions of its inputs. The gain
(Kd) for an XORPD is 4 because its output remains HIGH
(XORPDOUT = 1) for a phase error of one quarter cycle.
Similarly, Kd for the ECPD is 2 since its output remains HIGH
for a phase error of one half cycle. The type of phase detector
will determine the zero-phase-error point, i.e., the phase sep-
aration of the phase detector inputs for a φe defined to be
zero. For the basic DPLL system of Figure 3, φe = 0 when the
phase detector output is a square wave.
The XORPD inputs are one quarter cycle out-of-phase for
zero phase error. For the ECPD, φe = 0 when the inputs are
one half cycle out of phase.
The phase detector output controls the up/down input to the
K-counter. The counter is clocked by input frequency Mfc
which is a multiple M of the loop center frequency fc. When
the K-counter recycles up, it generates a carry pulse. Recy-
cling while counting down generates a borrow pulse. If the
carry and the borrow outputs are conceptually combined into
one output that is positive for a carry and negative for a bor-
row, and if the K-counter is considered as a frequency divider
with the ratio Mfc/K, the output of the K-counter will equal the
input frequency multiplied by the division ratio. Thus the out-
put from the K-counter is (KdφeMfc)/K.
The carry and borrow pulses go to the increment/decrement
(I/D) circuit which, in the absence of any carry or borrow
pulses has an output that is one half of the input clock (I/DCP).
The input clock is just a multiple, 2N, of the loop center fre-
quency. In response to a carry of borrow pulse, the I/D circuit
will either add or delete a pulse at I/DOUT. Thus the output of
the I/D circuit will be Nfc + (KdφeMfc)/2K.
The output of the N-counter (or the output of the phase-
locked-loop) is thus: fo = fc + (KdφeMfc)/2KN.
If this result is compared to the equation for a first-order ana-
log phase-locked-loop, the digital equivalent of the gain of the
VCO is just Mfc/2KN or fc/K for M = 2N.
Thus, the simple first-order phase-locked-loop with an adjust-
able K-counter is the equivalent of an analog phase-locked-
loop with a programmable VCO gain.
Functional Diagram
DCBA
4
KCP 6
D/U 3
ENCTR
5
I/DCP
9
φA1
10
φB
13
φA2
14 15 1 2
CARRY
MODULO-K BORROW
COUNTER
I/D
CKT
7
I/DOUT
J
Q
F/F
K
11
XORPDOUT
12
ECPDOUT
FUNCTION TABLE
EXCLUSIVE-OR PHASE DETECTOR
φA1
φB
XORPD OUT
L
L
L
L
H
H
H
L
H
H
H
L
FUNCTION TABLE
EDGE-CONTROLLED PHASE DETECTOR
φA2
H or L
φB
H or L
ECPD OUT
H
L
H or L
No Change
H or L
No Change
H = Steady-State High Level, L = Steady-State Low Level, = LOW
to HIGH φ Transition, = HIGH to LOW φ Transition
K-COUNTER FUNCTION TABLE
(DIGITAL CONTROL)
MODULO
D
C
B
A
(K)
L
L
L
L
Inhibited
L
L
L
H
23
L
L
H
L
24
L
L
H
H
25
L
H
L
L
26
L
H
L
H
27
L
H
H
L
28
L
H
H
H
29
H
L
L
L
210
H
L
L
H
211
H
L
H
L
212
H
L
H
H
213
H
H
L
L
214
H
H
L
H
215
H
H
H
L
216
H
H
H
H
217
2





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