Shift Register. CD54HC299 Datasheet

CD54HC299 Register. Datasheet pdf. Equivalent

Part CD54HC299
Description 8-Bit Universal Shift Register
Feature Data sheet acquired from Harris Semiconductor SCHS178C January 1998 - Revised May 2003 CD54HC299, C.
Manufacture etcTI
Datasheet
Download CD54HC299 Datasheet



CD54HC299
Data sheet acquired from Harris Semiconductor
SCHS178C
January 1998 - Revised May 2003
CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
[ /Title
(CD74
HC299
,
CD74
HCT29
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Uni-
versal
Shift
Features
• Buffered Inputs
• Four Operating Modes: Shift Left, Shift Right, Load
and Store
• Can be Cascaded for N-Bit Word Lengths
• I/O0 - I/O7 Bus Drive Capability and Three-State for
Bus Oriented Applications
• Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Pinout
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
S0 1
OE1 2
OE2 3
I/O6 4
I/O4 5
I/O2 6
I/O0 7
Q0 8
MR 9
GND 10
20 VCC
19 S1
18 DS7
17 Q7
16 I/O7
15 I/O5
14 I/O3
13 I/O1
12 CP
11 DS0
Description
The ’HC259 and ’HCT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O0
- I/O7) respond only to the low-to-high transition of the clock
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.
The three-state input/output I(/O) port has three modes of
operation:
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC299F3A
-55 to 125
20 Ld CERDIP
CD54HCT299F3A
-55 to 125
20 Ld CERDIP
CD74HC299E
-55 to 125
20 Ld PDIP
CD74HC299M
-55 to 125
20 Ld SOIC
CD74HC299M96
-55 to 125
20 Ld SOIC
CD74HCT299E
-55 to 125
20 Ld PDIP
CD74HCT299M
-55 to 125
20 Ld SOIC
CD74HCT299M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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CD54HC299
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299
Functional Diagram
CP OE1 OE2 MR
12
23
9
THREE-
STATE
CONTROL
20
VCC
7
I/O 0
6
BUS LINE
OUTPUTS
I/O 2
5
I/O 4
4
I/O 6
STANDARD
OUTPUT
Q0
8
1
S0
I/O
THREE-STATE
OUTPUTS
SHIFT
REGISTER
I/O
THREE-STATE
OUTPUTS
MODE SELECTION
13
I/O 1
14
I/O 3
15
I/O 5
BUS LINE
OUTPUTS
16
I/O7
17
Q7
STANDARD
OUTPUT
19
S1
10
GND
11 18
DS0 DS7
FUNCTION
Read Register
Load Register
Disable I/O
MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE
OE1
L
L
L
L
X
OE2
L
L
L
L
X
INPUTS
S0
S1
L
X
L
X
X
L
X
L
H
H
Qn (REGISTER)
L
H
L
H
Qn = I/On
H
X
X
X
X
X
H
X
X
X
INPUTS/OUTPUTS
I/O0 --- I/O7
L
H
L
H
I/On = Inputs
(Z)
(Z)
TRUTH TABLE
INPUTS
REGISTER OUTPUTS
FUNCTION
MR CP
S0
S1 DS0 DS7 I/On Q0
Q1
---
Q6 Q7
RESET (CLEAR)
L
X
X
X
X
X
X
L
L
---
L
L
Shift Right
Shift Left
Hold (Do Nothing)
Parallel Load
H
h
l
l
X
X
L
q0
---
q5
q6
H
h
l
h
X
X
H
q0
---
q5
Q6
H
l
h
X
l
X
q1
q2
---
q7
L
H
l
h
X
h
X
q1
q2
---
q7
H
H
l
l
X
X
X
q0
q1
---
q6
q7
H
h
h
X
X
l
L
L
---
L
L
H
h
h
X
X
h
H
H
---
H
H
H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input voltage
low one set-up time prior to clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to clock
transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, = Low to High Clock Transition.
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