CLOCK GENERATOR. HMC1034LP6GE Datasheet

HMC1034LP6GE GENERATOR. Datasheet pdf. Equivalent

Part HMC1034LP6GE
Description CLOCK GENERATOR
Feature Clock Genertors - SMT HMC1034LP6GE v01.0312 CLOCK GENERATOR WITH FRACTIONAL-N PLL & INTEGRATED VCO,.
Manufacture Analog Devices
Datasheet
Download HMC1034LP6GE Datasheet



HMC1034LP6GE
HMC1034LP6GE
v01.0312
CLOCK GENERATOR WITH FRACTIONAL-N PLL
& INTEGRATED VCO, 125 - 3000 MHz
Typical Applications
• 10G/40G/100G Optical Modules, Transponders,
Line Cards
• OTN and SONET/SDH Applications
• 1G/10G Ethernet Line Cards
• High Frequency Processor Clocks
• Low Jitter SAW Oscillator Replacement
• Fiber Channel Interface Clocks
• Cellular/4G Infrastructure
• DDS Replacement
• 10G Optical Modules, Transponders, Line Cards
Functional Diagram
Features
Frequency Range: 125 - 3000 MHz
78 fs RMS Jitter Generation (Typical)
Exceeds G.8251 & GR-253-CORE
Jitter Specifications
-165 dBc/Hz Phase Noise floor
Maximum Phase Detector Rate 100 MHz
Figure of Merit (FOM) -227 dBc/Hz
24-Bit Step Size, Resolution 3 Hz Typical
Exact Frequency Mode
Built-in Digital Self Test
40 Lead 6x6mm SMT Package: 36mm2
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Trademarks and registered trademarks arAe tphepplriocpearttyioofntheSir urepsppecotivret:owPnehrso. ne: 978-250-3A3p4p3licaotrionaSpuppsp@orht:iPtthitoen.ec: o1-m800-ANALOG-D



HMC1034LP6GE
HMC1034LP6GE
v01.0312
CLOCK GENERATOR WITH FRACTIONAL-N PLL
& INTEGRATED VCO, 125 - 3000 MHz
General Description
The HMC1034LP6GE is a low-noise, wide-band clock generator IC with a fractional-N Phase Locked Loop (PLL) that
features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between
125MHz and 3GHz range. The HMC1034LP6GE features low noise Phase Detector (PD) and Delta-Sigma modulator,
capable of operating at up to 100MHz, permit wider loop-bandwidths with excellent spectral performance.
The HMC1034LP6GE features industry leading phase noise and jitter performance, across the operating range,
that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior
noise floor (<-165dBc/Hz) makes the HMC1034LP6GE an ideal source for a variety of applications –such as clock
references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SERDES) circuits,
FPGAs and processors. The HMC1034LP6GE can also be used as an LO for 10G/40G/100G optical modules and
transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency
translation.
The differential output of the HMC1034LP6GE includes a 2-bit output amplitude control which may be set via the
SPI serial programming interface, and an output Mute function. The Delta-Sigma Modulator of the HMC1034LP6GE
features Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with close to 0Hz
frequency error.
For theory of operation and register map refer to the “PLLs with Integrated VCOs - RF VCOs Operating Guide”. To
view the Operating Guide, please visit www.hittite.com and choose HMC1034LP6GE from the “Search by Part
Number” pull down menu.
Electrical Specifications, VPPCP, VDDLS, VCC1, VCC2 = 5V; RVDD, AVDD,
DVDD3V, VCCPD, VCCHF, VCCPS = 3.3V Min & Max Specified across Temperature -40 °C to 85 °C
Parameter
RF Output Characteristics
Output Frequency
Output Specifications
Output Voltage
Output Amplitude Control
Output Common Mode Voltage
VCO Output Divider
VCO RF Divider Range
PLL RF Divider Characteristics
19-Bit N-Divider Range (Integer)
19-Bit N-Divider Range (Fractional)
REF Input Characteristics
Max Ref Input Frequency
Ref Input Voltage
Ref Input Capacitance
14-Bit R-Divider Range
Condition
Single-Ended Swing (peak-to-
peak), 50 Ohm termination
Gain Setting = 00, F=800 MHz
Gain Setting = 01, F=800 MHz
Gain Setting = 10, F=800 MHz
Gain Setting = 11, F=800 MHz
1,2,4,6,8,...,62
Max = 219 - 1
Fractional Nominal Divide Ratio
Varies (-3 / +4) Dynamically Max
AC Coupled [1]
Min.
Typ.
Max.
125
3000
0.25
1.35
300
450
685
1.1
AC Coupling Recommended
1
62
16
524,287
20
524,283
350
1
2
3.3
5
1
16,383
Units
MHz
Vpp
mVpp
mVpp
mVpp
Vpp
MHz
Vp-p
pF
[1] Measured with 100 Ω external termination. See Hittite PLL w/ Integraged VCOs Operating Guide Reference Input Stage section for
more details.
[2] Slew rate of greater or equal to 0.5 ns/V is recommended, see PLL with Integrated RF VCOs Operating Guide for more details.
Frequency is guaranteed across process voltage and temperature from -40 °C to 85 °C.
[3] This maximum phase detector frequency can only be achieved if the minimum N value is respected. eg. In the case of fractional feedback
mode, the maximum PFD rate = fvco/20 or 100 MHz, whichever is less.
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2
Trademarks and registered trademarks arAe tphepplriocpearttyioofntheSir urepsppecotivret:owPnehrso. ne: 978-250-3A3p4p3licaotrionaSpuppsp@orht:iPtthitoen.ec: o1-m800-ANALOG-D





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