SWITCH DRIVER/CONTROLLER. HMC677LP5E Datasheet

HMC677LP5E DRIVER/CONTROLLER. Datasheet pdf. Equivalent

Part HMC677LP5E
Description 6-Bit SERIAL/PARALLEL SWITCH DRIVER/CONTROLLER
Feature HMC677LP5 / 677LP5E v05.0810 6-Bit SERIAL/PARALLEL SWITCH DRIVER/CONTROLLER INTERFACE - SMT Typi.
Manufacture Analog Devices
Datasheet
Download HMC677LP5E Datasheet



HMC677LP5E
HMC677LP5 / 677LP5E
v05.0810
6-Bit SERIAL/PARALLEL SWITCH
DRIVER/CONTROLLER
Typical Applications
The HMC677LP5(E) is ideal for:
• Microwave and Millimeterwave Control Circuits
• Test and Measurement Equipment
• Complex Multi-Function Assemblies
• Military and Space Subsystems
• Transmit/Receive Module Controllers
5
Functional Diagram
Features
Accepts Serial or Parallel Data
Compatible with TTL and CMOS Logic
Complementary Outputs
6-Bit Control Word
Power-up State Selection
Low Power Consumption
Fast Clock Rate
General Description
The HMC677LP5(E) is a multi-function BiCMOS
control interface IC which is ideal for driving the gates
of FET and pHEMT based MMIC control devices.
This unique IC can be used to simplify the control
of microwave and millimeterwave transmit/receive
modules, military subsystems, and multi-throw/
multi-port test and measurement equipment. The
HMC677LP5(E) accepts serial or parallel data, and
can drive up to 6 complementary sets of outputs.
The HMC677LP5(E) also provides additional
functionality such as a power-up state selection,
adjustable output voltage levels, and a latched paral-
lel control mode which allows multiple control devices
to share a common data bus. The HMC677LP5(E)
is ideal for controlling digital phase shifters, digital
attenuators, digital variable gain amplifiers, and
switching matrices embedded in complex microwave
and millimeterwave assemblies.
Electrical Specifications, TA = +25° C, Vdd1 = Vdd2 = +5V, Vee = -5V, Voph = 0V
Parameter
Min
Typ
Max
Input High Voltage, Vih
2
-
-
Low Voltage, Vil
-
-
0.8
Output High Voltage, Voh (Ioh = 1 mA, Vee = -4.5V)
Voph - 0.1
-
-
Output Low Voltage, Vol (Iol = 2 mA, Vee = -4.5V)
-
-
Vee + 0.1
Maximum Input Leakage Current, Iin
-
-
1
Propagation Delay, tplh
-
-
80
Maximum Serial Bit Rate
-
-
10
Maximum I/O Update Rate
-
-
100
Units
V
V
V
V
µA
nS
Mbps
ns
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Trademarks and registered trademarks aArepthpelpircopaetrityoonf thSeiur rpesppeoctrivte: oPwhneorsn. e: 978-250-33A4p3plicoartioanpSpusp@pohrti:tPtihteo.nceo: 1m-800-ANALOG-D



HMC677LP5E
v05.0810
HMC677LP5 / 677LP5E
6-Bit SERIAL/PARALLEL SWITCH
DRIVER/CONTROLLER
Serial Control Interface
The HMC677LP5(E) contains a 3-wire SPI compatible digital interface (DATA, CLK, LE). It is activated when P/S
is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires
clean transitions. Standard logic families work well. When LE is high, 6-bit data in the serial input register is transferred
to the outputs. When LE is high CLK is masked to prevent data transition during output loading.
When P/S is low, 3-wire SPI interface inputs (DATA, CLK, LE) are disabled and the serial input register is loaded
asynchronously with parallel digital inputs (I0-I5). When LE is high, 6-bit parallel data is transferred.
For all modes of operations, the outputs will stay constant while LE is kept low.
5
Parameter
Typ.
Min. serial period, tSCK
Control set-up time, tCS
Control hold-time, tCH
LE setup-time, tLN
Min. LE pulse width, tLEW
Min LE pulse spacing, tLES
Serial clock hold-time from LE, tCKN
Hold Time, tPH.
Latch Enable Minimum Width, tLEN
Setup Time, tPS
100 ns
20 ns
20 ns
10 ns
10 ns
630 ns
10 ns
0 ns
10 ns
2 ns
Timing Diagram (Latched Parallel Mode)
Parallel Mode (Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode - Outputs are changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at
a logic high to control in this manner.
Latched Parallel Mode - Outputs are selected using the Control Voltage Inputs and set while the LE is in the Low
state. This will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is
pulsed. See timing diagram above for reference.
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Trademarks and registered trademarks aArepthpelpircopaetrityoonf thSeiur rpesppeoctrivte: oPwhneorsn. e: 978-250-33A4p3plicoartioanpSpusp@pohrti:tPtihteo.nceo: 1m-800-ANALOG-D
5-2





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