FRACTIONAL-N PLL. HMC836LP6CE Datasheet

HMC836LP6CE PLL. Datasheet pdf. Equivalent

Part HMC836LP6CE
Description FRACTIONAL-N PLL
Feature HMC836LP6CE v07.1211 FRACTIONAL-N PLL WITH INTEGRATED VCO, 3365 - 3705 MHz Features • RF Bandwidt.
Manufacture Analog Devices
Datasheet
Download HMC836LP6CE Datasheet



HMC836LP6CE
HMC836LP6CE
v07.1211
FRACTIONAL-N PLL WITH
INTEGRATED VCO, 3365 - 3705 MHz
Features
• RF Bandwidth: 3365 to 3705 MHz
• Ultra Low Phase Noise
-98 dBc/Hz in Band Typ
• Figure of Merit (FOM) -227 dBc
• < 180 fs rms Jitter
(Integrated 100 Hz to 100 MHz SSB)
• 24-bit Frequency Step Size,
Resolution 3 Hz typ
• Exact Frequency Mode
• Built-in Digital Self Test
• 40 Lead 6x6 mm SMT Package: 36 mm2
Typical Applications
7
• Cellular/4G Infrastructure
• Repeaters and Femtocells
• Communications Test Equipment
• CATV Equipment
Functional Diagram
• Phased Array Applications
• DDS Replacement
• Very High Data Rate Radios
7-1
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Trademarks and registered trademarks aArepthpelpircopaetrityoonf thSeiur rpesppeoctrivte: oPwhneorsn. e: 978-250-33A4p3plicoartioanpSpusp@pohrti:tPtihteo.nceo: 1m-800-ANALOG-D



HMC836LP6CE
HMC836LP6CE
v07.1211
FRACTIONAL-N PLL WITH
INTEGRATED VCO, 3365 - 3705 MHz
General Description
The HMC836LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) with an Integrated Voltage Controlled
Oscillator (VCO). The PLL consists of an integrated low noise VCO with x2 output, an autocalibration subsystem for
low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise
reference path divider and a fractional divider.
The fractional PLL features an advanced delta-sigma modulator design that allows both fine step sizes and low
spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency
hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency
hopping and low micro-phonics.
For theory of operation and register map refer to the “PLLs with Integrated VCOs - RF VCOs Operating Guide”. To
view the Operating Guide, please visit www.hittite.com and choose HMC836LP6CE from the “Search by Part
Number” pull down menu.
Electrical Specifications, TA = +25° C
VPPCP, VDDCP, VCC1, VCC2 = 5V ±4%; RVDD, AVDD, DVDD3V, VCCPD, VCCHF, VCCPS =
3.3V ±6% GNDCP = GNDLS = Ground Paddle = 0V
Parameter
RF Output Characteristics
VCO Frequency
RF Output Frequency at fVCO x2
RF Output Power at fVCO x2
VCO Tuning Sensitivity
VCO Supply Pushing
RF Output 2nd Harmonic
RF Output 3rd Harmonic
RF Output 4th Harmonic
RF Divider Characteristics
19-Bit N-Divider Range (Integer)
19-Bit N-Divider Range (Fractional)
REF Input Characteristics
Ref Input Frequency
Ref Input Range
Ref Input Capacitance
14-Bit R-Divider Range
Phase Detector (PD)
PD Frequency Fractional Feedback Mode
PD Frequency Fractional Feedforward
Mode (and Register 6 [17:16] = 10)
PD Frequency Integer Mode
Condition
Measured at 2 GHz, 2V
Measured at 2 GHz, 2V
Max = 219 - 1
Fractional nominal divide ratio
varies (-3 / +4) dynamically max
Synthesizer phase noise can
degrade by about 5dB when oper-
ating with a reference frequency
near the low end of this range.
AC Coupled
[1]
[1]
[1]
Min.
1682.5
3365
-1
-2
16
20
10
1.5
1
0.1
0.1
0.1
Typ.
Max.
Units
1852.5
MHz
3705
MHz
6
9
dBm
15
MHz/V
1.5
MHz/V
-25
dBc
-23
dBc
-31
dBc
524,287
524,283
50
200
MHz
2
3.3
Vpp
5
pF
16,383
100
MHz
80
MHz
125
MHz
Note 1: This maximum phase detector frequency can only be achieved if the minimum N value is respected. eg. In the case of fractional feedback
mode, the maximum PFD rate = fvco/20 or 100MHz, whichever is less.
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Trademarks and registered trademarks aArepthpelpircopaetrityoonf thSeiur rpesppeoctrivte: oPwhneorsn. e: 978-250-33A4p3plicoartioanpSpusp@pohrti:tPtihteo.nceo: 1m-800-ANALOG-D
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