CLOCK DIVIDER/DELAY. HMC988LP3E Datasheet

HMC988LP3E DIVIDER/DELAY. Datasheet pdf. Equivalent

Part HMC988LP3E
Description PROGRAMMABLE CLOCK DIVIDER/DELAY
Feature Clock Distribution - SMT HMC988LP3E v04.1014 PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typic.
Manufacture Analog Devices
Datasheet
Download HMC988LP3E Datasheet



HMC988LP3E
HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY
DC - 4 GHz
Typical Applications
The HMC988LP3E is ideal for:
Basestation Digital Pre-Distortion Paths(DPD)
High Performance Automated Test
Equipment(ATE)
Backplane clock skew management
Phase Coherence of multiple clock paths
Clock Delay management to improve setup &
hold time margins
PCB signal flight time offset circuits
Track and hold circuits for ADC/DACs
Functional Diagram
Features
DC - 4 GHz
-170 dBc/Hz floor @ 100 MHz output
-164 dBc/Hz floor @ 2 GHz output
Integrated Jitter 35 fsRMS@ 100 MHz output
13 fsRMS(calculated) @ 2 GHz output
Adjustable output phase with soft/hard reset sync
Adjustable output delay in 60 steps of 20 ps
Flexible Input Interface:
LVPECL,LVDS,CML,CMOS Compatible
AC or DC Coupling
On - Chip Termination 50 Ω (100 Ω Differential)
Output Driver (LVPECL):
800 mVpp LVPECL into 50 Ω Single-Ended (+3
dBm Fo)
Up to 8 addressable dividers per SPI bus
3.3 V operation or 5 V operation with Optional on-
chip regulator for best performance
3 x 3 QFN Leadless SMT Package
General Description
The HMC988LP3E is a an ultra low noise clock
divider capable of dividing by 1/2/4/8/16/32. It is a
versatile device with additional functionality including
adjustable output phase, adjustable delay in 60 steps
of ~ 20 ps, a clock synchronization function, and a
clock invert option.
Housed in a compact 3x3 mm SMT QFN package, the
clock divider offers a high level of functionality. The
device works with 3.3 V supply or may be connected
to 5 V supply and utilize the optional on-chip regulator.
This on-chip regulator may be bypassed.
Up to 8 addressable HMC988LP3E devices can be
used together on the SPI bus.
The HMC988LP3E is ideally suited for data converter
applications with extremely low phase noise
requirements.
1
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Trademarks and registered trademarks arAe tphepplriocpearttyioofntheSir urespppecotivret:owPnehrso. ne: 978-250-3A3p4p3licaotrionaSpuppsp@orht:iPtthitoen.ec: o1-m800-ANALOG-D



HMC988LP3E
HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY
DC - 4 GHz
Table 1. Electrical Specifications
Unless otherwise specified: T = +25 °C. Current consumptions assumes fine adjustable delay is disabled. Phase
noise degrades approximately 15 dB if using fine delay adjustment.
Parameter
Conditions
Min
Typ.
Max
Units
OSCP/N Input Frequency Range
DIVP/N Output Frequency Range
Divide Ratios
Maximum Fine Delay Adjust Frequency
VDD
VDD
Input Swing (LVPECL or AC)
Output Swing (LVPECL) [1]
Rise/Fall Time (LVPECL OUT)
with on-chip regulator
bypass on-chip regulator
Measured into a 50ohm
Load
Measured into a 50ohm
Load
20%/80%
DC
DC
DC
+3.7
+3.1
1/2/4/8/16/32
+4.5
+3.3
0.800
See Figure 9
0.8 (single ended)
1.6 (differential)
90
4
4
1
+5.5
+3.5
GHz
GHz
GHz
V
V
Vpp
Vpp
Vppd
ps
OSCP/N Input Commom Mode DC Bias [2]
+1.6
+2
+2.5
V
DIVP/N Output Common Mode Voltage [1]
+2
V
Phase Noise (@100 MHz offset)
[3]
@ 100 MHz output
@ 500 MHz output
@ 1 GHz output
@ 2 GHz output
Jitter Density
@ 100 MHz output
@ 500 MHz output
@ 1 GHz output
@ 2 GHz output
Integrated Jitter (12k - 20MHz)
@ 100 MHz output
@ 500 MHz output
@ 1 GHz output
@ 2 GHz output
[4]
[5]
[6]
[6]
[6]
FOM (Figure of Merit) Noise Floor
Noise Floor =
FOM+10Log(Fout)
Coarse Delay Adjustment Range
60 steps of ~ 20 ps;
Delay compresses with
increasing frequency.
Fine Delay Adjustment Range
[7] See Figure 6. With
300
divider bypassed maxi-
mum frequency limited to
650MHz
Fine Delay Adjustment Resolution
Fine Delay Adjustment Step Count
PSRR
[8]
With Regulator
AM
-70
PM
-80
-170
-168
-166
-164
7.1
1.8
1.1
0.7
32
8
5
3.2
-254
1/2 to ∞ *TINPUT
20
60
dBc/Hz
asec/√Hz
fsec
dBc/Hz
Input
Cycles
1500
ps
ps
-80
dBc
-92
dBc
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2
Trademarks and registered trademarks arAe tphepplriocpearttyioofntheSir urespppecotivret:owPnehrso. ne: 978-250-3A3p4p3licaotrionaSpuppsp@orht:iPtthitoen.ec: o1-m800-ANALOG-D





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