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PCA9539R Dataheets PDF



Part Number PCA9539R
Manufacturers NXP
Logo NXP
Description 16-bit I2C and SMBus low power I/O port
Datasheet PCA9539R DatasheetPCA9539R Datasheet (PDF)

PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 9 — 8 November 2017 Product data sheet 1. General description The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for A.

  PCA9539R   PCA9539R



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PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 9 — 8 November 2017 Product data sheet 1. General description The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity inversion register. All registers can be read by the system master. The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and a different address range. The PCA9539; PCA9539R open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. In the PCA9539, the RESET pin causes the same reset/default I/O input configuration to occur without de-powering the device, holding the registers and I2C-bus state machine in their default state until the RESET input is once again HIGH. This input requires a pull-up to VDD. In the PCA9539R however, only the device state machine is initialized by the RESET pin and the internal general-purpose registers remain unchanged. Using the PCA9539R RESET pin will only reset the I2C-bus interface should it be stuck LOW to regain access to the I2C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I2C-bus is being restored. Two hardware pins (A0, A1) vary the fixed I2C-bus address and allow up to four devices to share the same I2C-bus/SMBus. 2. Features and benefits  16-bit I2C-bus GPIO with interrupt and reset  Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9539PW/Q900 and PCA9539RPW/Q900)  5 V tolerant I/Os NXP Semiconductors PCA9539; PCA9539R 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset  Polarity inversion register  Active LOW interrupt output  Active LOW reset input  Low standby current  Noise filter on SCL/SDA inputs  No glitch on power-up  Internal power-on reset  16 I/O pins which default to 16 inputs  0 Hz to 400 kHz clock frequency  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Offered in three different packages: SO24, TSSOP24, and HVQFN24 3. Ordering information Table 1. Ordering information Type number Topside marking PCA9539BS 9539 Package Name HVQFN24 PCA9539RBS 539R HVQFN24 PCA9539D PCA9539D SO24 PCA9539PW PCA9539PW TSSOP24 PCA9539PW/Q900[1] PCA9539PW TSSOP24 PCA9539RPW PA9539RPW TSSOP24 PCA9539RPW/Q900[1] PA9539RPW TSSOP24 Description plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4  4  0.85 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4  4  0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT616-1 SOT616-1 SOT137-1 SOT355-1 SOT355-1 SOT355-1 SOT355-1 [1] PCA9539PW/Q900 and PCA9539RPW/Q900 are AEC-Q100 compliant. Contact [email protected] for PPAP. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number PCA9539BS PCA9539BS,115 PCA9539BS,118 PCA9539BSHP Package Packing method HVQFN24 Reel 7” Q1/T1 *standard mark SMD[1] HVQFN24 Reel 13” Q1/T1 *standard mark SMD[1] HVQFN24 Reel 13” Q2/T3 *standard mark SMD[2] Minimum Temperature order quantity 1500 Tamb = 40 C to +85 C 6000 Tamb = 40 C to +85 C 6000 Tamb = 40 C to +85 C PCA9539_PCA9539R Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 8 November 2017 © NXP Semiconductors N.V. 2017. All ri.


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