MC9S08PL16S

NXP Semiconductors Data Sheet: Technical Data Document Number MC9S08PL16S Rev. 3, 06/2020 MC9S08PL16S Data Sheet Supports: MC9S08PL16S and MC9S08PL8S Key features 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across operating temperature range – Supporting up to 30 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 1 KB random-access memory (RAM) – Flash and RAM access protection Power-saving modes – One low power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode Clocks – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution; 1% deviation across temperature range of 0 ºC to 70ºC, 1.5% deviation across temperature range of –40 ºC to 85 ºC; Up to 20 MHz – Oscillator (XOSC) — Loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset MC9S08PL16S Peripherals – ADC - 12-channel, 10-bit resolution; 2.5 µs conversion time; eight-level dat...