SAC57D54H

NXP Semiconductors Data Sheet: Technical Data Document Number SAC57D54H Rev. 7, 05/2017 SAC57D54H Features ARM™ Cortex-A5, 32-bit CPU – Supports ARMv7- ISA – 32 KB Instruction cache, 32 KB Data cache – NEON SIMD Media Processing Engine – FPU supporting double precision floating point operations – Memory Management Unit – GIC Interrupt Controller – Up to 320 MHz ARM™ Cortex-M4, 32-bit CPU – Supports ARMv7 - ISA – 16 KB Instruction cache, 16 KB Data cache – 64 KB Tightly-Coupled Memory (TCM) – Single Precision FPU – NVIC Interrupts Controller – 1.25 DMIPS per MHz integer performance – Up to 160 MHz I/O Processor – ARM™ Cortex-M0+, 32-bit CPU – Intelligent Stepper Motor Drive SAC57D54H Debug functionality – Run-time debug control of cores and visibility of system resources using the Debug Access Port (DAP) – IEEE 1149.1/ IEEE 1149.7 System JTAG Controller (SJTAG) – Program and Data Trace support (16-bit data width) implemented by the ARM Trace Port Interface Unit (TPIU) Trace capture Timer – Four 8-channel Flextimer modules (FTM) – Two 4 channel System Timer Module (STM) – Three Software WatchDog Timers (SWT) – One 8 channel Periodic Interrupt Timer (PIT) – Autonomous Real Time Counter (RTC) Analog – 1 x 24 channel, 12-bit analog-to-digital converter (ADC) – 2 analog comparators (CMP) Security – Cryptographic Services Engine (CSE) Memory subsystem – System Memory Protection Unit – 4 MB on-chip flash supported with the flash controller – 1 MB on-chip SRAM with...