MC9S12KG128

MC9S12KG128 Data Sheet HCS12 Microcontrollers MC9S12KG128 Rev. 1.16 06/2010 freescale.com To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual. Revision History Date June, 2010 Revision Level 1.16 Description Change SCI from V1 to V2, Chagne ATD from V1 to V3. Update TIM block guide. Update mask set Table 1-7, add Section 1.7 ATD External Trigger Input Connection Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1) . . . . . . . 17 Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1). . . . . . . 73 Chapter 3 2 Kbyte EEPROM Module (S12EETS2KV1) . . . . . . . . . . . . . . 117 Chapter 4 Port Integration Module (PIM9KG128V1) . . . . . . . . . . . . . . . . 137 Chapter 5 Clocks and Reset Generator (CRGV4) Block Description . . 177 Chapter 6 Pierce Oscillator (S12OSCLCPV1) . . . . . . . . . . . . . . . . . . . . . 213 Chapter 7 Analog-to-Digital Converter (ATD10B16CV3) . . . . . . . . . . . . 219 Chapter 8 Inter-Integrated Circuit (IICV2) . . . ...