74LX1G08

74LX1G08 LOW VOLTAGE CMOS SINGLE 2-INPUT AND GATE WITH 5V TOLERANT INPUT s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 4.5ns (MAX.) at VCC = 3V s LOW POWER DISSIPATION: ICC = 1µA (MAX.) at TA = 25°C s POWER DOWN PROTECTION ON INPUTS ) AND OUTPUTS t(s s SYMMETRICAL OUTPUT IMPEDANCE: c |IOH| = IOL = 24mA (MIN) at VCC = 3V u s BALANCED PROPAGATION DELAYS: rod tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: P VCC(OPR) = 1.65V to 5.5V te (1.2V Data Retention) le s IMPROVED LATCH-UP IMMUNITY so DESCRIPTION b The 74LX1G08 is a low voltage CMOS SINGLE O 2-INPUT AND GATE fabricated with sub-micron - silicon gate and double-layer metal wiring C2MOS t(s) technology. It is ideal for 1.65 to 5.5 VCC operations and low c power and low noise applications. The internal u circuit is composed of 3 stages including buffer SOT23-5L SOT323-5L ORDER CODES PACKAGE SOT23-5L SOT323-5L T&R 74LX1G08STR 74LX1G08CTR output, which provide high noise immunity and stable output. Power down protection is provided on input and output and 0 to 7V can be accepted on inputs with no regard to the supply voltage. It can be interfaced to 5V signal environment for inputs in mixed 3.3/5V system. All inputs and outputs are equipped with protection circuits against static discharge. Obsolete Prod PIN CONNECTION AND IEC LOGIC SYMBOLS April 2004 1/10 74LX1G08 INPUT AND OUTPUT EQUIVALENT CIRCUIT roduct(s) PIN DESCRIPTION P PIN N° te 1 le 2 o 3 bs 4 O 5 SYMBOL 1A 1B GND 1Y VCC NAME AND FUNCTION Data Input Data Input Gro...