Applications Processor. MIMX8QM6AVUFFAB Datasheet

MIMX8QM6AVUFFAB Processor. Datasheet pdf. Equivalent

Part MIMX8QM6AVUFFAB
Description Applications Processor
Feature NXP Semiconductors Data Sheet: Technical Data Document Number: IMX8QMAEC Rev. 0, 10/2019 MIMX8QMxAV.
Manufacture NXP
Datasheet
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MIMX8QM6AVUFFAB
NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8QMAEC
Rev. 0, 10/2019
MIMX8QMxAVUxxAx
i.MX 8QuadMax
Automotive and
Infotainment
Applications Processors
Package Information
29 x 29 mm package case outline
Ordering Information
See Table 2 on page 5
1 Introduction
The i.MX 8 Family consists of three processors:
i.MX 8QuadMax, 8QuadPlus, and 8DualMax. This data
sheet covers the i.MX 8QuadMax processor, which is
composed of eight cores (two Arm® Cortex®-A72, four
Arm Cortex®-A53, and two Arm Cortex®-M4F), dual
32-bit GPU subsystems, 4K H.265 capable VPU, and
dual failover-ready display controllers. This processor
supports a single 4K display (with multiple display
output options, including MIPI-DSI, HDMI, eDP/DP,
and LVDS), or multiple smaller displays. Memory
interfaces supporting LPDDR4, Quad SPI/Octal SPI
(FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide
range of peripheral I/Os such as PCIe 3.0, provide wide
flexibility. Advanced multicore audio processing is
supported by the Arm cores and a high performance
Tensilica® HiFi 4 DSP for pre- and post-audio
processing as well as voice recognition.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 System Controller Firmware (SCFW) Requirements5
1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 14
3.2 Recommended Connections for Unused Interfaces14
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Power supplies requirements and restrictions. . . . 27
4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . . 30
4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.7 Output Buffer Impedance Parameters. . . . . . . . . . 46
4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 51
4.9 General-Purpose Media Interface (GPMI) Timing . 54
4.10 External Peripheral Interface Parameters . . . . . . . 63
4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 121
5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 124
5.1 Boot mode configuration pins . . . . . . . . . . . . . . . 124
5.2 Boot devices interfaces allocation . . . . . . . . . . . . 125
6 Package information and contact assignments . . . . . . 127
6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 127
7 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of
its products.
© 2018-2019 NXP B.V.



MIMX8QM6AVUFFAB
Introduction
The i.MX 8QuadMax processor offers numerous advanced features as shown in this table.
Table 1. i.MX 8QuadMax advanced features
Function
Feature
Multicore architecture provides
4× Cortex-A53, 2× Cortex-A72 cores,
and 2× Cortex-M4F cores
Graphics Processing Unit (GPU)
Video Processing Unit (VPU)
Tensilica HiFi 4 DSP for pre- and
post-processing
Memory
AArch64 for 64-bit support and new architectural features
AArch32 for full backward compatibility with ARMv7
Cortex-A72 and Cortex-A53 cores support ARM virtualization extensions. sMMU
provides address virtualization to all subsystems.
Cortex-M4F cores for real-time applications
16× Vec4 shaders with 64 execution units. Split GPU architecture allows for dual
independent 8-Vec4 shader GPUs or a combined 16-Vec4 shader GPU.
Supports OpenGL 3.0, 2.1,; OpenGL ES 3.2, 3.1 (with AEP), 3.0, 2.0, and 1.1;
OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan
High-performance 2D Blit Engine
H.265 decode (4Kp60)
H.264 decode (4Kp30)
WMV9/VC-1 imple decode
MPEG 1 and 2 decode
AVS decode
MPEG4.2 ASP, H.263, Sorenson Spark decode
Divx 3.11 including GMC decode
ON2/Google VP6/VP8 decode
RealVideo 8/9/10 decode
JPEG and MJPEG decode
H.264 encode (1080p30)
666 MHz
Fixed-point and vector-floating-point support
32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and
64 KB of TCM)
64-bit LPDDR4 @1600 MHz
1× Quad SPI which can be used to connect to an FPGA
2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash
2× SD 3.0 card interfaces
1× eMMC5.1/SD3.0
RAW NAND (62-bit ECC support via BCH-62 module)
i.MX 8QuadMax Automotive and Infotainment Applications Processors, Rev. 0, 10/2019
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