level shifter. PTN3381B Datasheet

PTN3381B shifter. Datasheet pdf. Equivalent

Part PTN3381B
Description Enhanced performance HDMI/DVI level shifter
Feature PTN3381B Enhanced performance HDMI/DVI level shifter with voltage regulator, dongle detect support .
Manufacture NXP
Datasheet
Download PTN3381B Datasheet




PTN3381B
PTN3381B
Enhanced performance HDMI/DVI level shifter with voltage
regulator, dongle detect support and active DDC buffer
Rev. 2 — 15 October 2010
Product data sheet
1. General description
The PTN3381B is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the
PTN3381B provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel with active
buffering and level shifting of the DDC channel (consisting of a clock and a data line)
between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using
active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting
as well as disablement (isolation between source and sink) of the clock and data lines.
To provide the highest level of integration in external adapter (or: dongle) applications,
PTN3381B includes an onboard 5 V DC regulator. Its output is designed to provide the
required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for
a separate external regulator. The on-board regulator needs only two external capacitors
to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381B VDD
pins.
The low-swing AC-coupled differential input signals to the PTN3381B typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0
or HDMI v1.3a specification. By using PTN3381B, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure 1.
The PTN3381B main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of DisplayPort
Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal
capacitive isolation. Its I2C-bus control block also provides for optional software HDMI
dongle detect by issuing a predetermined code sequence upon a read command to an
I2C-bus specified address. The PTN3381B also supports power-saving modes in order to
minimize current consumption when no display is active or connected.
The PTN3381B is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3361B but provides an onboard 5 V regulator.



PTN3381B
NXP Semiconductors
PTN3381B
Fully integrated HDMI/DVI level shifter
PTN3381B is powered from a single 3.3 V power supply consuming a small amount of
power (100 mW typical without load at 5 V regulator output) and is offered in a 48-terminal
HVQFN48 package.
MULTI-MODE DISPLAY SOURCE
PCIe PHY ELECTRICAL
TMDS
PCIe
coded
output buffer
data TX
FF
TX
TMDS
PCIe
coded
output buffer
data TX
FF
TX
TMDS
PCIe
coded
output buffer
data TX
FF
TX
TMDS
PCIe
clock
output buffer
pattern TX
FF
TX
OE_N
PTN3381B
reconfigurable I/Os
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D4+
IN_D4
OUT_D4+
OUT_D4
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D3+
IN_D3
OUT_D3+
OUT_D3
AC-coupled
differential pair
TMDS data
DATA LANE
IN_D2+
IN_D2
OUT_D2+
OUT_D2
AC-coupled
differential pair
clock
CLOCK LANE
IN_D1+
IN_D1
OUT_D1+
OUT_D1
0 V to 3.3 V
HPD_SOURCE
3.3 V
DDC_EN
(0 V to 3.3 V)
0 V to 5 V
HPD_SINK
3.3 V
3.3 V
DDET
5V
CONFIGURATION
DDC I/O
(I2C-bus)
3.3 V
SCL_SOURCE
SCL_SINK
5V
SDA_SOURCE
SDA_SINK
V5OUT
5 VDC out
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1. Typical application system diagram
002aae076
PTN3381B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
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