MPC5606E

NXP Semiconductors Data Sheet: Technical Data Document Number: MPC5606E Rev. 4, 11/2019 MPC5606E MPC5606E Microcontroller Data Sheet NOTE For BCM89810 document please refer to Broadcom website and download the document Single issue, 32-bit CPU core complex (e200z0h) — Compliant with Power Architecture® embedded category — Variable Length Encoding (VLE) only Memory — 512 KB on-chip Code Flash with ECC and erase/program controller — additional 64 (4 × 16) KB on-chip Data Flash with ECC for EEPROM emulation — 96 KB on-chip SRAM with ECC Fail-safe protection — Programmable watchdog timer — Non-maskable interrupt — Fault collection unit Interrupts and events — 16-channel eDMA controller — 16 priority level controller — Up to 22 external interrupts — PIT implements four 32-bit timers — 120 interrupts are routed via INTC General purpose I/Os — Individually programmable as input, output or special function — 39 1 general purpose eTimer unit — 6 timers each with up/down capabilities 121 MAPBGA 8 mm x 8mm — 16-bit resolution, cascadeable counters — Quadrature decode with rotation direction flag — Double buffer input capture and output compare Communications interfaces — 2 LINFlex channels (1 × Master/Slave, 1 × Master Only) — 3 DSPI controllers with automatic chip select generation (up to 2/2/4 chip selects) — 1 FlexCAN interface (2.0B Active) with 32 message buffers One 10-bit analog-to-digital converter (ADC) — 7 input channels – 4 channels routed to the pins – 3 i...