16-BIT DIGITAL SIGNAL PROCESSOR
Freescale Semiconductor, Inc...
MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this documen...
Description
Freescale Semiconductor, Inc...
MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56167/D, Rev. 1
DSP56167
Advance Information
16-BIT DIGITAL SIGNAL PROCESSOR
P R E L I M I N A R Y The general-purpose, programmable DSP56167 is an enhanced version of the DSP56166 with
added features. Designed primarily for speech coding and digital communications, the DSP56167 has a built-in Σ∆ codec and Phase Lock Loop (PLL). This MPU-style DSP also contains memories and digital peripherals that provide a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCE™) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. This RAM-based DSP contains a 2 K × 16 Program RAM and a 4 K × 16 data RAM. The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56167. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The DSP56167 is a member of Motorola’s DSP56100 family of 16-bit Digital Signal Processors (DSPs).
Port A
Port B or
Host
15
7+10
Codec, Port C and/or SSI0, SSI1, Timer EXTAL SXFC CLKO
Address Generation
Unit Peripheral Address Generation
Unit
On-Chip Peripherals: Host, SSI0, SSI1, Timer GPIO, Codec
Internal ...
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