2:1/1:2 Mux/Buffer. DS100MB203 Datasheet

DS100MB203 Mux/Buffer. Datasheet pdf. Equivalent

Part DS100MB203
Description 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer
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DS100MB203
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Sample &
Buy
Technical
Documents
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Software
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DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer
With Equalization and De-Emphasis
1 Features
1 10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or
Fan-Out
• Low 390 mW Total Power (Typical)
• Advanced Signal Conditioning Features:
– Receive Equalization Up to 36 dB at 5 GHz
– Transmit De-Emphasis Up to –12 dB
– Transmit Output Voltage Control: 600 mV to
1300 mV
• Programmable Through Pin Selection, EEPROM
or SMBus Interface
• Selectable 2.5-V or 3.3-V Supply Voltage
• –40°C to 85°C Operating Temperature Range
2 Applications
• 10GE, 10G-KR
• PCIe Gen-1/2/3
• SAS2/SATA3 (Up to 6 Gbps)
• XAUI, RXAUI
3 Description
The DS100MB203 device is a dual port 2:1
multiplexer and 1:2 switch or fan-out buffer with
signal conditioning suitable for 10GE, 10G-KR
(802.3ap), Fibre Channel, PCIe, Infiniband,
SATA3/SAS2 and other high-speed bus applications
with data rates up to 10.3125 Gbps.
The continuous time linear equalizer (CTLE) of the
receiver provides necessary boost to compensate up
to 40” FR-4 or 10m cable (AWG-24) at 10.3125 Gbps
- This on-chip feature eliminates the need for external
signal conditioners. The transmitter features a
programmable amplitude voltage levels to be
selectable from 600 mVp-p to 1300 mVp-p and De-
Emphasis of up to 12 dB.
The DS100MB203 can be configured to support
PCIe, SAS/SATA, 10G-KR or other signaling
protocols. When operating in 10G-KR and PCIe Gen-
3 mode, the DS100MB203 transparently allows the
host controller and the end point to optimize the full
link and negotiate transmit equalizer coefficients. This
seamless management of the link training protocol
ensures system level interoperability with minimum
latency.
The programmable settings can be applied through
pin settings, SMBus (I2C) protocol or loaded directly
from an external EEPROM. When operating in the
EEPROM mode, the configuration information is
automatically loaded on power up, which eliminates
the need for an external microprocessor or software
driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS100MB203
WQFN (54)
10.00 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Functional Block Diagram
MB203
D_OUT+
D_OUT-
Address straps
(pull-up to VIN or
pull-down to
GND)(1)
D_IN+
D_IN-
AD0
AD1
AD2
AD3
1 OF 2
SMBus Slave Mode(1)
SMBus Slave Mode(1)
S3M.3BVu(3s) Slave Mode(1)
10 F 1 F
0.1 F
(x5)
SEL0
READ_EN / SEL1
ALL_DONE
VIN (3.3 V)
VDD_SEL
VDD (2.5 V)
S_INA+
S_INA-
S_INB+
S_INB-
S_OUTA+
S_OUTA-
S_OUTB+
S_OUTB-
MODE
ENSMB
SDA(2)
SCL(2)
INPUT_EN
RESET
GND (DAP)
GND
SATA/SAS
Mode(4)
VIN
SMBus Slave
Mode(1)
To SMBus/I2C
Host Controller
SEL0
EXPANDER
RX
TX
RX
TX
SEL1
Typical Application
MB203
D_OUT0
S_INA0
S_INB0
DRIVE 0
TXA_0
DRIVE 1
TXB_0
D_OUT1
S_INA1
S_INA1
TXA_1
TXB_1
D_IN0
D_IN1
S_OUTA0
S_OUTB0
S_OUTA1
S_OUTB1
RXA_0
RXB_0
RXA_1
RXB_1
(1) Schematic shows connection for SMBus Slave Mode (ENSMB = 1 k: to VIN)
For SMBus Master Mode or Pin Mode configuration, the connections are different.
(2) SMBus signals must be pulled up elsewhere in the system.
(3) Schematic requires different connections for 2.5 V mode.
(4) Schematic requires pullup resistor for 10G-KR Mode.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



DS100MB203
DS100MB203
SNLS396D – JANUARY 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Electrical Characteristics – Serial Management Bus
Interface .................................................................. 11
6.7 Timing Requirements – Serial Bus Interface .......... 11
6.8 Typical Characteristics ............................................ 13
7 Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 15
7.5 Programming .......................................................... 19
7.6 Register Maps ......................................................... 20
8 Application and Implementation ........................ 40
8.1 Application Information............................................ 40
8.2 Typical Application .................................................. 41
9 Power Supply Recommendations...................... 42
9.1 Power Supply Bypassing ........................................ 42
10 Layout................................................................... 44
10.1 Layout Guidelines ................................................. 44
10.2 Layout Example .................................................... 45
11 Device and Documentation Support ................. 46
11.1 Documentation Support ........................................ 46
11.2 Community Resources.......................................... 46
11.3 Trademarks ........................................................... 46
11.4 Electrostatic Discharge Caution ............................ 46
11.5 Glossary ................................................................ 46
12 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2015) to Revision D
Page
• Changed Signal detect pattern at 8 Gbps .............................................................................................................................. 8
Changes from Revision B (April 2013) to Revision C
Page
• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Application
and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical,
Packaging, and Ordering Information .................................................................................................................................... 1
Changes from Revision A (April 2013) to Revision B
Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2
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