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SN54LV165A Dataheets PDF



Part Number SN54LV165A
Manufacturers Texas Instruments
Logo Texas Instruments
Description Parallel-Load 8-Bit Shift Register
Datasheet SN54LV165A DatasheetSN54LV165A Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54LV165A, SN74LV165A SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016 SNx4LV165A Parallel-Load 8-Bit Shift Registers 1 Features •1 2-V to 5.5-V VCC Operation • Max tpd of 10.5 ns at 5 V • Support Mixed-Mode Voltage Operation on All Ports • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 20.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54LV165A, SN74LV165A SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016 SNx4LV165A Parallel-Load 8-Bit Shift Registers 1 Features •1 2-V to 5.5-V VCC Operation • Max tpd of 10.5 ns at 5 V • Support Mixed-Mode Voltage Operation on All Ports • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • IP Routers • Enterprise Switches • Access Control and Security: Access Keypads and Biometrics • Smart Meters: Power Line Communication 3 Description The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation. When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output, QH. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SNx4LV165AD SOIC (16) 9.90 mm × 3.91 mm SNx4LV165ADB SSOP (16) 6.20 mm × 5.30 mm SNx4LV165ANS SO (16) 10.30 mm × 5.30 mm SNx4LV165APW TSSOP (16) 5.00 mm × 4.40 mm SNx4LV165ADGV TVSOP (16) 3.60 mm × 4.40 mm SNx4LV165ARGY VQFN (16) 4.00 mm × 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 1 SH/LD Logic Diagram (Positive Logic) A B C D E F G H 11 12 13 14 3 4 5 6 15 CLK INH 2 CLK 10 SER S C1 1D S C1 1D S C1 1D S C1 1D S C1 1D S C1 1D S C1 1D S C1 1D 9 QH 7 QH R R R R R R R R 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54LV165A, SN74LV165A SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Pin Configuration and Functions ......................... 3 6 Specifications......................................................... 4 6.1 Absolute Maximum Ratings ...................................... 4 6.2 ESD Ratings.............................................................. 4 6.3 Recommended Operating Conditions....................... 5 6.4 Thermal Information .................................................. 5 6.5 Electrical Characteristics........................................... 6 6.6 Timing Requirements—VCC = 2.5 V ± 0.2 V............. 7 6.7 Timing Requirements—VCC = 3.3 V ± 0.3 V............. 7 6.8 Timing Requirements—VCC = 5 V ± 0.5 V................ 8 6.9 Switching Characteristics—VCC = 2.5 V ± 0.2 V..... 10 6.10 Switching Characteristics—VCC = 3.3 V ± 0.3 V... 11 6.11 Switching Characteristics—VCC = 5 V ± 0.5 V...... 12 6.12 Operating Characteristics...................................... 12 6.13 Typical Characteristics .......................................... 13 7 Parameter Measurement Information ................ 14 8 Detailed Description ............................................ 15 8.1 Overview ................................................................. 15 8.2 Functional Block Diagram ....................................... 15 8.3 Feature Description................................................. 16 8.4 Device Functional Modes........................................ 17 9 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application .................................................. 18 10 Power Supply Recommendations ..................... 20 11 Layout................................................................... 20 11.1 Layout Guid.


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