SN74LV161284

SN74LV161284 19-BIT BUS INTERFACE SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002 D 4.5-V to 5.5-V VCC Operation D 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors D Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 250 mA Per JEDEC 17 D ESD Protection Exceeds JESD 22 – 4000-V Human-Body Model (A114-A) – 300-V Machine Model (A115-A) – 2000-V Charged-Device Model (C101) description/ordering information The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. DGG OR DL PACKAGE (TOP VIEW) HD 1 A9 2 A10 3 A11 4 A12 5 A13 6 VCC 7 A1 8 A2 9 GND 10 A3 11 A4 12 A5 13 A6 14 GND 15 A7 16 A8 17 VCC 18 PERI LOGIC IN 19 A14 20 A15 21 A16 22 A17 23 HOST LOGIC OUT 24 48 DIR 47 Y9 46 Y10 45 Y11 44 Y12 43 Y13 42 VCC CABLE 41 B1 40 B2 39 GND 38 B3 37 B4 36 B5 35 B6 34 GND 33 B7 32 B8 31 VCC CABLE 30 PERI LOGIC OUT 29 ...