D-TYPE FLIP-FLOPS. SN54LV174A Datasheet

SN54LV174A FLIP-FLOPS. Datasheet pdf. Equivalent

Part SN54LV174A
Description HEX D-TYPE FLIP-FLOPS
Feature D 2-V to 5.5-V VCC Operation D Max tpd of 8.5 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V.
Manufacture etcTI
Datasheet
Download SN54LV174A Datasheet




SN54LV174A
D 2-V to 5.5-V VCC Operation
D Max tpd of 8.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV174A, SN74LV174A
HEX DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS401G − APRIL 1998 − REVISED APRIL 2005
SN54LV174A . . . J OR W PACKAGE
SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1D 3
2D 4
2Q 5
3D 6
3Q 7
GND 8
16 VCC
15 6Q
14 6D
13 5D
12 5Q
11 4D
10 4Q
9 CLK
SN54LV174A . . . FK PACKAGE
(TOP VIEW)
description/ordering information
The ’LV174A devices are hex D-type flip-flops
designed for 2-V to 5.5-V VCC operation.
These devices are positive-edge-triggered
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going edge of the
clock pulse. When the clock (CLK) input is at
either the high or low level, the D-input signal has
no effect at the output.
3 2 1 20 19
1D 4
18 6D
2D 5
17 5D
NC 6
16 NC
2Q 7
15 5Q
3D 8
14 4D
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 40
Reel of 2500
SN74LV174AD
SN74LV174ADR
LV174A
SOP − NS
Reel of 2000 SN74LV174ANSR 74LV174A
−40°C to 85°C
SSOP − DB
Reel of 2000
Tube of 90
SN74LV174ADBR
SN74LV174APW
LV174A
TSSOP − PW
Reel of 2000
Reel of 250
SN74LV174APWR
SN74LV174APWT
LV174A
TVSOP − DGV Reel of 2000 SN74LV174ADGVR LV174A
CDIP − J
−55°C to 125°C CFP − W
Tube of 25
Tube of 150
SNJ54LV174AJ
SNJ54LV174AW
SNJ54LV174AJ
SNJ54LV174AW
LCCC − FK
Tube of 55
SNJ54LV174AFK
SNJ54LV174AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
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SN54LV174A
SN54LV174A, SN74LV174A
HEX DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS401G − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
1
CLR
9
CLK
3
1D
FUNCTION TABLE
INPUTS
CLR CLK D
OUTPUT
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
1D
C1
R
2
1Q
To Five Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265







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