D-TYPE FLIP-FLOPS. SN74LV175A Datasheet

SN74LV175A FLIP-FLOPS. Datasheet pdf. Equivalent

Part SN74LV175A
Description QUADRUPLE D-TYPE FLIP-FLOPS
Feature D 2-V to 5.5-V VCC Operation D Max tpd of 7.5 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V.
Manufacture etcTI
Datasheet
Download SN74LV175A Datasheet



SN74LV175A
D 2-V to 5.5-V VCC Operation
D Max tpd of 7.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Contain Four Flip-Flops With Double-Rail
Outputs
D Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’LV175A devices are quadruple D-type
flip-flops designed for 2-V to 5.5-V VCC operation.
These devices have a direct clear (CLR) input and
feature complementary outputs from each
flip-flop.
SN54LV175A, SN74LV175A
QUADRUPLE DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS400G − APRIL 1998 − REVISED APRIL 2005
SN54LV175A . . . J OR W PACKAGE
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
16 VCC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 CLK
SN54LV175A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1Q 4
18 4Q
1D 5
17 4D
NC 6
16 NC
2D 7
15 3D
2Q 8
14 3Q
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
Tube of 40
Reel of 2500
SN74LV175AD
SN74LV175ADR
LV175A
SOP − NS
Reel of 2000 SN74LV175ANSR 74LV175A
−40°C to 85°C
SSOP − DB
Reel of 2000
Tube of 90
SN74LV175ADBR
SN74LV175APW
LV175A
TSSOP − PW
Reel of 2000
Reel of 250
SN74LV175APWR
SN74LV175APWT
LV175A
TVSOP − DGV Reel of 2000 SN74LV175ADGVR LV175A
CDIP − J
Tube of 25
SNJ54LV175AJ
SNJ54LV175AJ
−55°C to 125°C CFP − W
Tube of 150
SNJ54LV175AW
SNJ54LV175AW
LCCC − FK
Tube of 55
SNJ54LV175AFK
SNJ54LV175AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2005, Texas Instruments Incorporated
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SN74LV175A
SN54LV175A, SN74LV175A
QUADRUPLE DĆTYPE FLIPĆFLOPS
WITH CLEAR
SCLS400G − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR CLK D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Q0 Q0
logic diagram (positive logic)
1
CLR
9
CLK
4
1D
1D
C1
R
2
1Q
3
1Q
To Three Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265







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