A/D Converter. ADC08100 Datasheet

ADC08100 Converter. Datasheet pdf. Equivalent

Part ADC08100
Description A/D Converter
Feature ADC08100 www.ti.com SNAS060I – JUNE 2000 – REVISED MAY 2013 ADC08100 8-Bit, 20 Msps to 100 Msps, .
Manufacture etcTI
Datasheet
Download ADC08100 Datasheet




ADC08100
ADC08100
www.ti.com
SNAS060I – JUNE 2000 – REVISED MAY 2013
ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter
Check for Samples: ADC08100
FEATURES
1
2 Single-ended Input
• Internal Sample-and-hold Function
• Low Voltage (Single +3V) Operation
• Small Package
• Power-down Feature
APPLICATIONS
• Flat Panel Displays
• Projection Systems
• Set-top Boxes
• Battery-powered Instruments
• Communications
• Medical Scan Converters
• X-ray Imaging
• High Speed Viterbi Decoders
• Astronomy
KEY SPECIFICATIONS
• Resolution 8 bits
• Maximum Sampling Frequency 100 Msps (Min)
• DNL 0.4 LSB (Typ)
• ENOB 7.4 Bits (Typ) at fIN = 41 MHz
• THD –60 dB (Typ)
• Power Consumption
– Operating 1.3 mW/Msps (Typ)
– Power Down: 1 mW (Typ)
DESCRIPTION
The ADC08100 is a low-power, 8-bit, monolithic
analog-to-digital converter with an on-chip track-and-
hold circuit. Optimized for low cost, low power, small
size and ease of use, this product operates at
conversion rates of 20 Msps to 100 Msps with
outstanding dynamic performance over its full
operating range while consuming just 1.3 mW per
MHz of clock frequency. That's just 130 mW of power
at 100 Msps. Raising the PD pin puts the ADC08100
into a Power Down mode where it consumes just 1
mW.
The unique architecture achieves 7.4 Effective Bits
with 41 MHz input frequency. The excellent DC and
AC characteristics of this device, together with its low
power consumption and single +3V supply operation,
make it ideally suited for many imaging and
communications applications, including use in
portable equipment. Furthermore, the ADC08100 is
resistant to latch-up and the outputs are short-circuit
proof. The top and bottom of the ADC08100's
reference ladder are available for connections,
enabling a wide range of input possibilities. The
digital outputs are TTL/CMOS compatible with a
separate output power supply pin to support
interfacing with 3V or 2.5V logic. The digital inputs
(CLK and PD) are TTL/CMOS compatible. The output
format is straight binary
The ADC08100 is offered in a 24-lead plastic
package (TSSOP) and is specified over the industrial
temperature range of 40°C to +85°C.
PIN CONFIGURATION
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated



ADC08100
ADC08100
SNAS060I – JUNE 2000 – REVISED MAY 2013
Block Diagram
VA
DR VD
(pin 18)
www.ti.com
VRT
1
COARSE/FINE
COMPARATORS
17 ENCODER
& ERROR
CORRECTION
8
VRM
17
SWITCHES
8
8
MUX
OUTPUT
DRIVERS
DATA
OUT
256
COARSE/FINE
COMPARATORS
17 ENCODER
& ERROR
CORRECTION
8
VRB
CLOCK
GEN
Pin No.
Symbol
CLK
VIN
VIN GND
AGND
PD
DR GND
(pin 17)
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Equivalent Circuit
Description
6
VIN
Analog signal input. Conversion range is VRB to VRT.
3
VRT
9
VRM
10
VRB
VD
23
PD
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
VRB inputs define the VIN conversion range. Bypass well. See
THE ANALOG INPUT for more information.
Mid-point of the reference ladder. This pin should be bypassed
to a clean, quiet point in the analog ground plane with a 0.1
µF capacitor.
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
Power Down input. When this pin is high, the converter is in
the Power Down mode and the data output pins hold the last
conversion result.
24
CLK
DGND
CMOS/TTL compatible digital clock Input. VIN is sampled on
the falling edge of CLK input.
2
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Copyright © 2000–2013, Texas Instruments Incorporated







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