A/D Converter. ADC083000 Datasheet

ADC083000 Converter. Datasheet pdf. Equivalent

Part ADC083000
Description Low Power A/D Converter
Feature ADC083000 www.ti.com SNAS358N – JUNE 2006 – REVISED JULY 2009 ADC083000 8-Bit, 3 GSPS, High Perfo.
Manufacture etcTI
Datasheet
Download ADC083000 Datasheet




ADC083000
ADC083000
www.ti.com
SNAS358N – JUNE 2006 – REVISED JULY 2009
ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter
Check for Samples: ADC083000
FEATURES
1
2 Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Serial Interface for Extended Control
• Adjustment of Input Full-Scale Range and
Offset
• Duty Cycle Corrected Sample Clock
• Test Pattern
APPLICATIONS
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-Top Boxes
• Communications Systems
• Test Instrumentation
KEY SPECIFICATIONS
• Resolution 8 Bits
• Max Conversion Rate 3 GSPS (min)
• Error Rate 10-18 (typ)
• ENOB @ 748 MHz Input 7.0 Bits (typ)
• SNR @ 748 MHz 44.5 dB (typ)
• Full Power Bandwidth 3 GHz (typ)
• Power Consumption
– Operating 1.9 W (typ)
– Power Down Mode 25 mW (typ)
DESCRIPTION
The ADC083000 is a single, low power, high
performance CMOS analog-to-digital converter that
digitizes signals to 8 bits resolution at sampling rates
up to 3.4 GSPS. Consuming a typical 1.9 Watts at 3
GSPS from a single 1.9 Volt supply, this device is
specified to have no missing codes over the full
operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the self-
calibration scheme enable an excellent response of
all dynamic parameters up to Nyquist, producing a
high 7.0 Effective Number Of Bits, (ENOB) with a 748
MHz input signal and a 3 GHz sample rate while
providing a 10-18 Word Error Rate. The ADC083000
achieves a 3 GSPS sampling rate by utilizing both the
rising and falling edge of a 1.5 GHz input clock.
Output formatting is offset binary and the LVDS
digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode
voltage between 0.8V and 1.15V.
The ADC has a 1:4 demultiplexer that feeds four
LVDS buses and reduces the output data rate on
each bus to a quarter of the sampling rate.
The converter typically consumes less than 25 mW in
the Power Down Mode and is available in a 128-lead,
thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C TA +85°C)
temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated



ADC083000
ADC083000
SNAS358N – JUNE 2006 – REVISED JULY 2009
Block Diagram
+
S/H
-
VIN+
VIN-
+
S/H
-
VBG
CLK+
CLK-
Control
Inputs
Serial
Interface
VREF
3
www.ti.com
8-BIT
ADC1
8
DEMUX
LATCH
Dd
Data Bus Output
16 LVDS Pairs
Db
8-BIT
ADC2
CLK/2
2
Control
Logic
8
DEMUX
LATCH
Dc
Data Bus Output
16 LVDS Pairs
Da
DEMUX
Output
Clock
Generator
DCLK+
DCLK-
OR
CalRun
2
Submit Documentation Feedback
Product Folder Links: ADC083000
Copyright © 2006–2009, Texas Instruments Incorporated







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)