A/D Converter. ADC08500 Datasheet

ADC08500 Converter. Datasheet pdf. Equivalent

Part ADC08500
Description 8-Bit A/D Converter
Feature ADC08500 www.ti.com SNAS373E – MAY 2007 – REVISED APRIL 2013 ADC08500 High Performance, Low Power.
Manufacture etcTI
Datasheet
Download ADC08500 Datasheet



ADC08500
ADC08500
www.ti.com
SNAS373E – MAY 2007 – REVISED APRIL 2013
ADC08500 High Performance, Low Power 8-Bit, 500 MSPS A/D Converter
Check for Samples: ADC08500
FEATURES
1
2 Internal Sample-and-Hold
• Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Multiple ADC Synchronization Capability
• Ensured No Missing Codes
• Serial Interface for Extended Control
• Fine Adjustment of Input Full-Scale Range and
Offset
• Duty Cycle Corrected Sample Clock
APPLICATIONS
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-top Boxes
• Communications Systems
• Test Instrumentation
KEY SPECIFICATIONS
• Resolution 8 Bits
• Max Conversion Rate 500 MSPS (min)
• Bit Error Rate 10-18 (typ)
• ENOB @ 250 MHz Input 7.5 Bits (typ)
• DNL ±0.15 LSB (typ)
• Power Consumption
– Operating 0.8 W (typ)
– Power Down Mode 3.5 mW (typ)
DESCRIPTION
The ADC08500 is a low power, high performance
CMOS analog-to-digital converter that digitizes
signals to 8 bits resolution at sampling rates up to
500 MSPS. Consuming a typical 0.8 Watts at 500
MSPS from a single 1.9 Volt supply, this device is
ensured to have no missing codes over the full
operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the self-
calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a
high 7.5 ENOB with a 250 MHz input signal and a
500 MHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS
digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode
voltage between 0.8V and 1.2V.
The converter has a 1:2 demultiplexer that feeds two
LVDS buses and reduces the output data rate on
each bus to half the sampling rate.
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a 128-
lead, thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C TA +85°C)
temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated



ADC08500
ADC08500
SNAS373E – MAY 2007 – REVISED APRIL 2013
Block Diagram
VIN+
VIN-
+
S/H
-
VBG
VREF
CLK+
CLK-
Control
Inputs
Serial
Interface
3
8-BIT
ADC
CLK/2
2
Control
Logic
Figure 1.
www.ti.com
1:2 DEMUX
& LATCH
DOUT
DOUTD
Data Bus Output
16 LVDS Pairs
Output
Clock
Generator
DCLK+
DCLK-
OR
CalRun
2
Submit Documentation Feedback
Product Folder Links: ADC08500
Copyright © 2007–2013, Texas Instruments Incorporated







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)