A/D Converter. ADC088S102 Datasheet

ADC088S102 Converter. Datasheet pdf. Equivalent

Part ADC088S102
Description 8-Bit A/D Converter
Feature ADC088S102 www.ti.com SNAS339B – SEPTEMBER 2005 – REVISED MARCH 2013 ADC088S102 8-Channel, 500 kS.
Manufacture etcTI
Datasheet
Download ADC088S102 Datasheet




ADC088S102
ADC088S102
www.ti.com
SNAS339B – SEPTEMBER 2005 – REVISED MARCH 2013
ADC088S102 8-Channel, 500 kSPS to 1 MSPS, 8-Bit A/D Converter
Check for Samples: ADC088S102
FEATURES
1
2 Eight Input Channels
• Variable Power Management
• Independent Analog and Digital Supplies
• SPI/QSPI/MICROWIRE/DSP Compatible
• Packaged in 16-Lead TSSOP
APPLICATIONS
• Automotive Navigation
• Portable Systems
• Medical Instruments
• Mobile Communications
• Instrumentation and Control Systems
KEY SPECIFICATIONS
• Conversion Rate: 500 kSPS to 1 MSPS
• DNL (VA = VD = 5.0 V): ±0.3 LSB (max)
• INL (VA = VD = 5.0 V): ±0.2 LSB (max)
• Power Consumption
– 3V Supply: 1.8 mW (typ)
– 5V Supply: 8.0 mW (typ)
DESCRIPTION
The ADC088S102 is a low-power, eight-channel
CMOS 8-bit analog-to-digital converter specified for
conversion throughput rates of 500 kSPS to 1 MSPS.
The converter is based on a successive-
approximation register architecture with an internal
track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is
compatible with several standards, such as SPI,
QSPI, MICROWIRE, and many common DSP serial
interfaces.
The ADC088S102 may be operated with independent
analog and digital supplies. The analog supply (VA)
can range from +2.7V to +5.25V, and the digital
supply (VD) can range from +2.7V to VA. Normal
power consumption using a +3V or +5V supply is 1.8
mW and 8.0 mW, respectively. The power-down
feature reduces the power consumption to 0.03 µW
using a +3V supply and 0.15 µW using a +5V supply.
The ADC088S102 is packaged in a 16-lead TSSOP
package. Operation is specified over the extended
industrial temperature range of 40°C to +105°C.
Connection Diagram
CS
VA
AGND
IN0
IN1
IN2
IN3
IN4
1
16
2
15
3
14
4
13
ADC088S102
5
12
6
11
7
10
8
9
SCLK
DOUT
DIN
VD
DGND
IN7
IN6
IN5
Figure 1. 16-Lead TSSOP
See Package Number PW0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated



ADC088S102
ADC088S102
SNAS339B – SEPTEMBER 2005 – REVISED MARCH 2013
Block Diagram
IN0
.
.
MUX
.
IN7
T/H
AGND
ADC088S102
10-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
VA
AGND
VD
SCLK
CS
DIN
DOUT
DGND
www.ti.com
Pin No.
ANALOG I/O
4 - 11
DIGITAL I/O
16
Symbol
IN0 to IN7
SCLK
15
DOUT
14
DIN
1
CS
POWER SUPPLY
2
VA
13
VD
3
AGND
12
DGND
Pin Descriptions and Equivalent Circuits
Equivalent Circuit
Description
Analog inputs. These signals can range from 0V to VREF.
Digital clock input. The specified performance range of frequencies
for this input is 8 MHz to 16 MHz. This clock directly controls the
conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on
the falling edges of the SCLK pin.
Digital data input. The ADC088S102's Control Register is loaded
through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Conversions continue as long as CS is held low.
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet +2.7V to
+5.25V source and bypassed to GND with 1 µF and 0.1 µF
monolithic ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a +2.7V
to VA supply, and bypassed to GND with a 0.1 µF monolithic ceramic
capacitor located within 1 cm of the power pin.
The ground return for the analog supply and signals.
The ground return for the digital supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: ADC088S102







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)