A/D Converter. ADC08D1000 Datasheet

ADC08D1000 Converter. Datasheet pdf. Equivalent

Part ADC08D1000
Description Dual 8-Bit A/D Converter
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ADC08D1000
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ADC08D1000
SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015
ADC08D1000 High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
1 Features
1 Internal Sample-and-Hold
• Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Interleave Mode for 2x Sampling Rate
• Multiple ADC Synchronization Capability
• Ensured No Missing Codes
• Serial Interface for Extended Control
• Fine Adjustment of Input Full-Scale Range and
Offset
• Duty Cycle Corrected Sample Clock
2 Applications
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-top boxes
• Communications Systems
• Test Instrumentation
3 Key Specifications
• Resolution: 8 Bits
• Max Conversion Rate: 1 GSPS (min)
• Bit Error Rate: 10-18 (typ)
• ENOB @ 500 MHz Input: 7.4 Bits (typ)
• DNL: ±0.15 LSB (typ)
• Power Consumption
– Operating: 1.6 W (typ)
– Power Down Mode: 3.5 mW (typ)
4 Description
The ADC08D1000 is a dual, low power, high
performance CMOS analog-to-digital converter that
digitizes signals to 8 bits resolution at sampling rates
up to 1.3 GSPS. Consuming a typical 1.6 Watts at 1
GSPS from a single 1.9 Volt supply, this device is
ensured to have no missing codes over the full
operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the self-
calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a
high 7.4 ENOB with a 500 MHz input signal and a 1
GHz sample rate while providing a 10-18 B.E.R.
Output formatting is offset binary and the LVDS
digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode
voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds
two LVDS buses and reduces the output data rate on
each bus to half the sampling rate. The two
converters can be interleaved and used as a single 2
GSPS ADC.
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a 128-
lead, thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C TA +85°C)
temperature range.
Patenting Notice:
The Texas Instruments products covered by this
datasheet are protected by at least the following U.S.
patents: Pat. No. 6,847,320; Pat. No. 7,015,729; Pat.
No. 7,068,195; and Pat. No. 7,088,281. This list of
patents may not be all inclusive, and the products
covered by this datasheet may be protected by
additional issued patents and patents pending both in
the U.S. and elsewhere in the world. A copy of this
datasheet including the patent list noted here is also
available
on
the
Internet
www.ti.com/lit/gpn/adc08d1000. This is intended to
serve as notice under 35 U.S.C. § 287(a).
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



ADC08D1000
ADC08D1000
SNAS248I – SEPTEMBER 2004 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Key Specifications ................................................. 1
4 Description ............................................................. 1
5 Revision History..................................................... 2
6 Block Diagram........................................................ 3
7 Pin Configuration................................................... 4
8 Absolute Maximum Ratings.................................. 8
9 Operating Ratings.................................................. 9
10 Package Thermal Resistance............................... 9
11 Converter Electrical Characteristics ................... 9
11.1 Specification Definitions ........................................ 15
11.2 Transfer Characteristic.......................................... 17
11.3 TEST CIRCUIT DIAGRAMS ................................. 17
12 Typical Performance Characteristics................ 20
13 Functional Description ....................................... 25
13.1 OVERVIEW........................................................... 25
13.2 NORMAL/EXTENDED CONTROL........................ 28
13.3 THE SERIAL INTERFACE.................................... 30
13.4 REGISTER DESCRIPTION .................................. 31
13.5 MULTIPLE ADC SYNCHRONIZATION ................ 35
14 APPLICATIONS INFORMATION ......................... 36
14.1 THE REFERENCE VOLTAGE.............................. 36
14.2 THE ANALOG INPUT ........................................... 36
14.3 THE CLOCK INPUTS ........................................... 38
14.4 CONTROL PINS ................................................... 39
14.5 THE DIGITAL OUTPUTS...................................... 43
14.6 POWER CONSIDERATIONS ............................... 43
14.7 LAYOUT AND GROUNDING................................ 45
14.8 DYNAMIC PERFORMANCE................................. 46
14.9 USING THE SERIAL INTERFACE ....................... 46
14.10 COMMON APPLICATION PITFALLS ................. 47
15 Device and Documentation Support ................. 48
15.1 Trademarks ........................................................... 48
15.2 Electrostatic Discharge Caution ............................ 48
15.3 Glossary ................................................................ 48
16 Mechanical, Packaging, and Orderable
Information ........................................................... 48
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2013) to Revision I
Page
• Added Patenting Notice ......................................................................................................................................................... 1
Changes from Revision G (April 2013) to Revision H
Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 47
2
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