A/D Converter. ADC08D1500 Datasheet

ADC08D1500 Converter. Datasheet pdf. Equivalent

Part ADC08D1500
Description Dual 8-Bit A/D Converter
Feature ADC08D1500 www.ti.com SNAS316G – JUNE 2005 – REVISED APRIL 2013 ADC08D1500 High Performance, Low .
Manufacture etcTI
Datasheet
Download ADC08D1500 Datasheet



ADC08D1500
ADC08D1500
www.ti.com
SNAS316G – JUNE 2005 – REVISED APRIL 2013
ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter
Check for Samples: ADC08D1500
FEATURES
1
2 Internal Sample-and-Hold
• Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Interleave Mode for 2x Sample Rate
• Multiple ADC Synchronization Capability
• Ensured No Missing Codes
• Serial Interface for Extended Control
• Fine Adjustment of Input Full-Scale Range and
Offset
• Duty Cycle Corrected Sample Clock
APPLICATIONS
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-Top Boxes
• Communications Systems
• Test Instrumentation
KEY SPECIFICATIONS
• Resolution 8 Bits
• Max Conversion Rate 1.5 GSPS (min)
• Error Rate 10-18 (typ)
• ENOB @ 748 MHz Input 7.25 Bits (typ)
• DNL ±0.15 LSB (typ)
• Power Consumption
– Operating 1.8 W (typ)
– Power Down Mode 3.5 mW (typ)
DESCRIPTION
The ADC08D1500 is a dual, low power, high
performance CMOS analog-to-digital converter that
digitizes signals to 8 bits resolution at sample rates
up to 1.7 GSPS. Consuming a typical 1.8 Watts at
1.5 GSPS from a single 1.9 Volt supply, this device is
ensured to have no missing codes over the full
operating temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the self-
calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing a
high 7.25 ENOB with a 748 MHz input signal and a
1.5 GHz sample rate while providing a 10-18 C.E.R.
Output formatting is binary and the LVDS digital
outputs are compatible with IEEE 1596.3-1996, with
the exception of an adjustable common mode voltage
between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds
two LVDS buses and reduces the output data rate on
each bus to half the sample rate. The two converters
can be interleaved and used as a single 3 GSPS
ADC.
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a 128-
lead, thermally enhanced exposed pad HLQFP and
operates over the Industrial (-40°C TA +85°C)
temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated



ADC08D1500
ADC08D1500
SNAS316G – JUNE 2005 – REVISED APRIL 2013
Block Diagram
VINI+
VINI-
VINQ+
VINQ-
+
S/H
-
INPUT
MUX
+
S/H
-
VBG
VREF
CLK+
CLK-
Control
Inputs
Serial
Interface
3
8-BIT
ADC
www.ti.com
I CHANNEL
1:2 DEMUX
& LATCH
DIOUT
DIOUTD
Data Bus Output
16 LVDS Pairs
8-BIT
ADC
Q CHANNEL
1:2 DEMUX
& LATCH
DQOUT
DQOUTD
Data Bus Output
16 LVDS Pairs
CLK/2
2
Control
Logic
Output
Clock
Generator
DCLK+
DCLK-
OR
CalRun
2
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