A/D Converter. ADC08D1520 Datasheet

ADC08D1520 Converter. Datasheet pdf. Equivalent

Part ADC08D1520
Description 8-Bit A/D Converter
Feature ADC08D1520 www.ti.com SNAS357D – APRIL 2008 – REVISED MARCH 2013 ADC08D1520 Low Power, 8-Bit, Dua.
Manufacture etcTI
Datasheet
Download ADC08D1520 Datasheet



ADC08D1520
ADC08D1520
www.ti.com
SNAS357D – APRIL 2008 – REVISED MARCH 2013
ADC08D1520 Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
Check for Samples: ADC08D1520
FEATURES
1
2 Single +1.9V ±0.1V Operation
• Interleave Mode for 2x Sample Rate
• Multiple ADC Synchronization Capability
• Adjustment of Input Full-Scale Range, Clock
Phase, and Offset
• Choice of SDR or DDR Output Clocking
• 1:1 or 1:2 Selectable Output Demux
• Second DCLK Output
• Duty Cycle Corrected Sample Clock
• Test Pattern
APPLICATIONS
• Direct RF Down Conversion
• Digital Oscilloscopes
• Satellite Set-top boxes
• Communications Systems
• Test Instrumentation
KEY SPECIFICATIONS
• Resolution: 8 Bits
• Max Conversion Rate: 1.5 GSPS (max)
• Code Error Rate: 10-18 (typ)
• ENOB @ 748 MHz Input: 7.4 Bits (typ)
• DNL: ±0.15 LSB (typ)
• Power Consumption (Non-DES Mode)
– Operating in Non-Demux Mode:1.6 W (typ)
– Operating in 1:2 Demux Mode: 2.0 W (typ)
– Power Down Mode: 3.5 mW (typ)
DESCRIPTION
The ADC08D1520 is a dual, low power, high
performance CMOS analog-to-digital converter that
builds upon the ADC08D1500 platform. The
ADC08D1520 digitizes signals to 8 bits of resolution
at sample rates up to 1.7 GSPS. It has expanded
features compared to the ADC08D1500, which
include a test pattern output for system debug, a
clock phase adjust, and selectable output
demultiplexer modes. Consuming a typical 1.6 Watts
in Non-Demultiplex Mode at 1.0 GSPS from a single
1.9 Volt supply, this device is guaranteed to have no
missing codes over the full operating temperature
range. The unique folding and interpolating
architecture, the fully differential comparator design,
the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a
very flat response of all dynamic parameters beyond
Nyquist, producing a high 7.4 Effective Number of
Bits (ENOB) with a 748 MHz input signal and a 1.5
GHz sample rate while providing a 10-18 Code Error
Rate (C.E.R.) Output formatting is offset binary and
the Low Voltage Differential Signaling (LVDS) digital
outputs are compatible with IEEE 1596.3-1996, with
the exception of an adjustable common mode voltage
between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer
which feeds two LVDS buses. If the 1:2
Demultiplexed Mode is selected, the output data rate
is reduced to half the input sample rate on each bus.
When Non-Demultiplexed Mode is selected, the
output data rate on channels DI and DQ is at the
same rate as the input sample clock. The two
converters can be interleaved and used as a single 3
GSPS ADC.
The converter typically consumes less than 3.5 mW
in the Power Down Mode and is available in a leaded
or lead-free, 128-pin, thermally enhanced, HLQFP
and operates over the Industrial (-40°C TA +85°C)
temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated



ADC08D1520
ADC08D1520
SNAS357D – APRIL 2008 – REVISED MARCH 2013
Block Diagram
VINI+
VINI-
+
S/H
-
INPUT
MUX
VINQ+
VINQ-
+
S/H
-
VBG
CLK+
CLK-
Control
Inputs
Serial
Interface
VREF
3
www.ti.com
8-BIT
ADC1
8
Selectable
DI
DEMUX
LATCH
Data Bus Output
DId
16 LVDS Pairs
8-BIT
ADC2
CLK/2
2
Control
Logic
8
DQ
Selectable
DEMUX
LATCH
DQd
Data Bus Output
16 LVDS Pairs
DEMUX
Output
Clock
Generator
DCLK+
DCLK-
OR/DCLK2
CalRun
2
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