A/D Converter. ADC08DL500 Datasheet

ADC08DL500 Converter. Datasheet pdf. Equivalent

Part ADC08DL500
Description Dual 8-Bit A/D Converter
Feature ADC08DL500 www.ti.com SNAS495C – MARCH 2011 – REVISED MARCH 2011 ADC08DL500 Low Power, 8-Bit, Dua.
Manufacture etcTI
Datasheet
Download ADC08DL500 Datasheet



ADC08DL500
ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter
Check for Samples: ADC08DL500
FEATURES
1
2 Single +1.9V ±0.1V Operation
• Duty Cycle Corrected Sample Clock
APPLICATIONS
• Satellite Modems
• Digital Oscilloscopes
• Direct RF Down Conversion
• Communications Systems
• Test Instrumentation
DESCRIPTION
The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500
digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in
demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing
codes over the full operating temperature range. The unique folding and interpolating architecture, the fully
differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration
schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective
Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 1018 Code
Error Rate (C.E.R.)
The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead
LQFP and operates over the modified Industrial (-40°C TA +70°C) temperature range.
Resolution
Max Conversion Rate
Code Error Rate
ENOB @ 125 MHz Input
DNL
Power Consumption
Table 1. Key Specifications
Operating in 1:2 Demux Output
Power Down Mode
VALUE
8
500
1018
7.2
±0.15
1.25
3.3
UNIT
Bits
MSPS
(typ)
Bits (typ)
LSB (typ)
W (typ)
mW (typ)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated



ADC08DL500
ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Block Diagram
VINI+
VINI-
+
S/H
-
VINQ+
VINQ-
VBG
CLK+
CLK-
Control
Inputs
Serial
Interface
+
S/H
-
VREF
3
www.ti.com
8-BIT
ADC1
8
Selectable
DEMUX
LATCH
DI
DId
Data Bus Output
16 LVDS Pairs
8-BIT
ADC2
CLK/2
2
Control
Logic
8
DQ
Selectable
DEMUX
LATCH
DQd
Data Bus Output
16 LVDS Pairs
DEMUX
Output
Clock
Generator
DCLK+
DCLK-
OR/DCLK2
CalRun
2
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Copyright © 2011, Texas Instruments Incorporated







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