A/D Converter. ADC08DL502 Datasheet

ADC08DL502 Converter. Datasheet pdf. Equivalent

Part ADC08DL502
Description Dual 8-Bit A/D Converter
Feature ADC08DL502 www.ti.com SNAS582B – MARCH 2012 – REVISED MARCH 2013 Low Power, 8-Bit, Dual 500 MSPS .
Manufacture etcTI
Datasheet
Download ADC08DL502 Datasheet




ADC08DL502
ADC08DL502
www.ti.com
SNAS582B – MARCH 2012 – REVISED MARCH 2013
Low Power, 8-Bit, Dual 500 MSPS A/D Converter
Check for Samples: ADC08DL502
FEATURES
1
2 Single +1.9V ±0.1V Operation
• Duty Cycle Corrected Sample Clock
KEY SPECIFICATIONS
• Resolution: 8 Bits
• Max Conversion Rate: 500 MSPS
• Code Error Rate: 1018 (typ)
• ENOB @ 125 MHz Input: 7.5 Bits (typ)
• DNL: ±0.15 LSB (typ)
• Power Consumption
– Operating in 1:2 Demux Output: 1.25W (typ)
– Power Down Mode: 3.3 mW (typ)
APPLICATIONS
• Satellite Modems
• Digital Oscilloscopes
• Direct RF Down Conversion
• Communications Systems
• Test Instrumentation
DESCRIPTION
The ADC08DL502 is a dual, low power, high
performance, CMOS analog-to-digital converter. The
ADC08DL502 digitizes signals to 8 bits of resolution
at sample rates up to 500 MSPS. Consuming a
typical 1.2 Watts in demultiplex mode at 500 MSPS
from a single 1.9 Volt supply, this device is ensured
to have no missing codes over the full operating
temperature range. The unique folding and
interpolating architecture, the fully differential
comparator design, the innovative design of the
internal sample-and-hold amplifier and the calibration
schemes enable a very flat response of all dynamic
parameters beyond Nyquist, producing a high 7.5
Effective Number of Bits (ENOB) with a 125 MHz
input signal and a 500 MHz sample rate while
providing a 1018 Code Error Rate (C.E.R.)
The converter typically consumes 3.3 mW in the
Power Down Mode and is available in a lead-free
144-lead LQFP and operates over the modified
Industrial (-40°C TA +70°C) temperature range.
Block Diagram
VINI+
VINI-
+
S/H
-
8-BIT
ADC1
8
Selectable
DEMUX
LATCH
DI
DId
Data Bus Output
16 LVDS Pairs
VINQ+
VINQ-
VBG
+
S/H
-
VREF
8-BIT
ADC2
8
Selectable
DEMUX
LATCH
DQ
DQd
Data Bus Output
16 LVDS Pairs
CLK+
CLK-
CLK/2
2
Output
Clock
Generator
DCLK+
DCLK-
Control
Inputs
Serial
Interface
3
1
Control
Logic
DEMUX
OR/DCLK2
CalRun
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated



ADC08DL502
ADC08DL502
SNAS582B – MARCH 2012 – REVISED MARCH 2013
Pin Configuration
NC 1
GND 2
GND 3
VA 4
OutV/SCLK 5
OutEdge/DDR/SDATA 6
VA 7
GND 8
VCMO 9
VA 10
GND 11
VINI- 12
VINI+ 13
GND 14
VA 15
FSR/ALT_ECE/DCLK_RST- 16
DCLK_RST/DCLK_RST+ 17
VA 18
VA 19
CLK+ 20
CLK- 21
VA 22
GND 23
VINQ+ 24
VINQ- 25
GND 26
VA 27
PD 28
GND 29
VA 30
PDQ 31
CAL 32
VBG 33
REXT 34
GND 35
NC 36
ADC08DL502
www.ti.com
108 NC
107 DR GND
106 DI2+
105 DI2-
104 DI3+
103 DI3-
102 DI4+
101 DI4-
100 DI5+
99 DI5-
98 VDR
97 DR GND
96 DI6+
95 DI6-
94 DI7+
93 DI7-
92 DCLK+
91 DCLK-
90 OR-/DCLK2-
89 OR+/DCLK2+
88 DQ7-
87 DQ7+
86 DQ6-
85 DQ6+
84 DR GND
83 VDR
82 DQ5-
81 DQ5+
80 DQ4-
79 DQ4+
78 DQ3-
77 DQ3+
76 DQ2-
75 DQ2+
74 DR GND
73 NC
2
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