ADC08DL502

ADC08DL502 www.ti.com SNAS582B – MARCH 2012 – REVISED MARCH 2013 Low Power, 8-Bit, Dual 500 MSPS A/D Converter Check for Samples: ADC08DL502 FEATURES 1 2 Single +1.9V ±0.1V Operation Duty Cycle Corrected Sample Clock KEY SPECIFICATIONS Resolution: 8 Bits Max Conversion Rate: 500 MSPS Code Error Rate: 10−18 (typ) ENOB @ 125 MHz Input: 7.5 Bits (typ) DNL: ±0.15 LSB (typ) Power Consumption – Operating in 1:2 Demux Output: 1.25W (typ) – Power Down Mode: 3.3 mW (typ) APPLICATIONS Satellite Modems Digital Oscilloscopes Direct RF Down Conversion Communications Systems Test Instrumentation DESCRIPTION The ADC08DL502 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL502 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 Effective Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10−18 Code Error Rate (C.E.R.) The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 1...