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SN74LVC1G10 Dataheets PDF



Part Number SN74LVC1G10
Manufacturers Texas Instruments
Logo Texas Instruments
Description Single 3-Input Positive-NAND Gate
Datasheet SN74LVC1G10 DatasheetSN74LVC1G10 Datasheet (PDF)

SN74LVC1G10 www.ti.com SCES486E – SEPTEMBER 2003 – REVISED DECEMBER 2013 Single 3-Input Positive-NAND Gate Check for Samples: SN74LVC1G10 FEATURES 1 •2 Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max tpd of 3.8 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Insertion, Partial-Power- Down Mode, and Back Drive Protection • Latch-Up.

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SN74LVC1G10 www.ti.com SCES486E – SEPTEMBER 2003 – REVISED DECEMBER 2013 Single 3-Input Positive-NAND Gate Check for Samples: SN74LVC1G10 FEATURES 1 •2 Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Provides Down Translation to VCC • Max tpd of 3.8 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Insertion, Partial-Power- Down Mode, and Back Drive Protection • Latch-Up Performance Exceeds 100 mA per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged Device Model (C101) DESCRIPTION The SN74LVC1G10 performs the Boolean function Y = A • B • C or Y = A + B + C in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DBV PACKAGE (TOP VIEW) A 1 6 GND 2 5 DCK PACKAGE (TOP VIEW) C A 1 6C GND 2 5 VCC VCC B 3 4Y YZP PACKAGE (BOTTOM VIEW) B 34 GND 2 5 A 16 Y VCC C B 3 4 Y DRY PACKAGE (TOP VIEW) A1 GND 2 B3 6C 5 VCC 4Y See mechanical drawings for dimensions. DSF PACKAGE (TOP VIEW) A1 6 C GND 2 5 VCC B3 4 Y 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated SN74LVC1G10 SCES486E – SEPTEMBER 2003 – REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Function Table INPUTS A B C OUTPUT Y H H H L L X X H X L X H X X L H Logic diagram (Positive Logic) A B Y C Absolute Maximum Ratings(1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range VI Input voltage range(2) VO Voltage range applied to any output in the high-impedance or power-off state(2) VO Voltage range applied to any output in the high or low state(2) (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IO Continuous output current Continuous current through VCC or GND DBV package θJA Package thermal impedance(4) DCK package YZP package –0.5 6.5 V –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 V –50 mA –50 mA ±50 mA ±100 mA 165 259 °C/W 123 Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD 51-7. 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: SN74LVC1G10 SN74LVC1G10 www.ti.com SCES486E – SEPTEMBER 2003 – REVISED DECEMBER 2013 Recommended Operating Conditions(1) MIN MAX UNIT VCC Supply voltage Operating Data retention only 1.65 5.5 V 1.5 VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3 V 0.65 × VCC 1.7 V 2 0.7 × VCC 0.35 × VCC 0.7 V 0.8 0.3 × VCC 0 5.5 V 0 VCC V –4 –8 –16 mA –24 IOL Low-level output current VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3 V –32 4 8 16 mA 24 Δt/Δv Input transition rise or fall rate TA Operating free-air temperature VCC = 4.5 V VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 32 20 10 ns/V 10 –40 125 °C (1) All unused inputs of the device must be held at VCC or GND t.


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