ADC32J45

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADC32J42, ADC32J43, ADC32J44, ADC32J45 SBAS663A – MAY 2014 – REVISED JUNE 2015 ADC32J4x Dual-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converters with JESD204B Interface 1 Features 1 Dual Channel 14-Bit Resolution Single Supply: 1.8 V Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 72.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz Ultralow Power Consumption: – 227 mW/Ch at 160 MSPS Channel Isolation: 105 dB Internal Dither JESD204B Serial Interface: – Subclass 0, 1, 2 Compliant up to 3.2 Gbps – Supports One Lane per ADC up to 160 MSPS Support for Multichip Synchronization Pin-to-Pin Compatible with 12-Bit Version (ADC32J2X) Package: VQFN-48 (7 mm × 7 mm) 2 Applications Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software-Defined Radios (SDRs) Quadrature and Diversity Radio Receivers 3 Description The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analogto-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF...