RF Transceiver. ADRV9002 Datasheet

ADRV9002 Transceiver. Datasheet pdf. Equivalent

Part ADRV9002
Description Dual Narrow/Wideband RF Transceiver
Feature Preliminary Technical Data Dual Narrow/Wideband RF Transceiver ADRV9002 FEATURES 2 × 2 highly inte.
Manufacture Analog Devices
Datasheet
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Preliminary Technical Data Dual Narrow/Wideband RF Transcei ADRV9002 Datasheet
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ADRV9002
Preliminary Technical Data
Dual Narrow/Wideband RF Transceiver
ADRV9002
FEATURES
2 × 2 highly integrated transceiver
Frequency range of 30 MHz to 6000 MHz
Transmitter and receiver bandwidth up to 40 MHz
Fully integrated, fractional-N, RF synthesizers
LVDS and CSSI
Low power monitor and sleep modes
Multichip synchronization capabilities
FFH
Dynamic profile switching for dynamic data rates and
sample rates
Fully integrated DPD for narrowband and wideband
waveforms
Fully programmable via a 4-wire SPI
12 mm × 12 mm, 196-ball CSP_BGA
APPLICATIONS
Mission critical communications
Very high frequency (VHF), ultrahigh frequency (UHF), and
cellular to 6 GHz
Time division duplexing (TDD) and frequency division
duplexing (FDD) applications
GENERAL DESCRIPTION
The ADRV9002 is a highly integrated, RF transceiver that has
dual-channel transmitters, dual-channel receivers, integrated
synthesizers, and digital signal processing functions.
The IC delivers a versatile combination of high performance
and low power consumption required by battery powered radio
equipment and can operate in both FDD and TDD modes. The
ADRV9002 operates from 30 MHz to 6000 MHz and covers the
UHF, VHF, licensed and unlicensed cellular bands, and
industrial, scientific, and medical (ISM) bands. The IC can
support both narrowband and wideband standards up to
40 MHz bandwidth on both receive and transmit.
The transceiver consists of direct conversion signal paths with
state of the art noise figure and linearity. Each complete
receiver and transmitter subsystem includes dc offset
correction, quadrature error correction, and programmable
digital filters, which eliminate the need for these functions in
the digital baseband. In addition, several auxiliary functions
such as auxiliary analog-to-digital converters (ADCs), auxiliary
digital-to-analog converters (DACs), and general-purpose
input/outputs (GPIOs) are integrated to provide additional
monitoring and control capability.
The fully integrated phase-locked loops (PLLs) provide high
performance, low power, fractional-N frequency synthesis for
the transmitter, receiver, and clock sections. Careful design and
layout techniques provide the isolation required in high
performance personal radio applications.
All voltage controlled oscillator (VCO) and loop filter
components are integrated to minimize the external
component count. The local oscillators (LOs) have flexible
configuration options and include fast lock modes.
The transceiver includes low power sleep and monitor modes
to save power and extend the battery life of portable devices
while monitoring communication.
The fully integrated, low power digital predistortion (DPD) is
optimized for both narrowband and wideband signals and
enables linearization of high efficiency power amplifiers.
The ADRV9002 core can be powered directly from 1.0 V, 1.3 V,
and 1.8 V regulators and is controlled via a standard 4-wire
serial port. Other voltage supplies are used to provide proper
digital interface levels and to optimize receiver, transmitter, and
auxiliary converter performance.
High data rate and low data rate interfaces are supported using
configurable complementary metal-oxide semiconductors
(CMOS) or low voltage differential signaling (LVDS) serial
synchronous interface (SSI) choice. The ADRV9002 is
packaged in a 12 mm × 12 mm, 196-ball chip scale package ball
grid array (CSP_BGA).
Rev. PrA
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ADRV9002
ADRV9002
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 3
Specifications .................................................................................... 4
Transmitter Specifications .......................................................... 4
Receiver Specifications ................................................................ 6
Internal LO, External LO, and Device Clock ......................... 13
Digital Interfaces and Auxiliary Converters........................... 14
Power Supply Specifications ..................................................... 15
Current Consumption Estimates (Typical Values)............... 16
Timing Specifications ................................................................ 18
Absolute Maximum Ratings ......................................................... 20
Reflow Profile.............................................................................. 20
Thermal Resistance .................................................................... 20
Electrostatic Discharge (ESD) Ratings .................................... 20
ESD Caution................................................................................ 20
Pin Configuration and Function Descriptions .......................... 21
Typical Performance Characteristics........................................... 27
30 MHz Band .............................................................................. 27
Preliminary Technical Data
470 MHz Band............................................................................ 34
900 MHz Band............................................................................ 39
2400 MHz Band.......................................................................... 44
3500 MHz Band.......................................................................... 49
5800 MHz Band.......................................................................... 55
Phase Noise ................................................................................. 60
Theory of Operation ...................................................................... 62
Transmitter ................................................................................. 62
Receiver ....................................................................................... 63
DPD.............................................................................................. 64
Clock Input ................................................................................. 64
Synthesizers................................................................................. 64
SPI Interface................................................................................ 65
GPIO Pins ................................................................................... 65
Auxillary Converters.................................................................. 65
JTAG Boundary Scan ................................................................ 66
Applications Information ............................................................. 67
Power Supply Sequence............................................................. 67
Digital Data Interface ................................................................ 67
Outline Dimensions....................................................................... 71
Rev. PrA | Page 2 of 71





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