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SN74HCT377 Dataheets PDF



Part Number SN74HCT377
Manufacturers Texas Instruments
Logo Texas Instruments
Description OCTAL D-TYPE FLIP-FLOPS
Datasheet SN74HCT377 DatasheetSN74HCT377 Datasheet (PDF)

D Operating Voltage Range of 4.5 V to 5.5 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Inputs Are TTL-Voltage Compatible SN54HCT377 . . . J OR W PACKAGE SN74HCT377 . . . DW OR N PACKAGE (TOP VIEW) SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 D Contain Eight Flip-Flops With Single-Rail Outputs D Clock Enable Lat.

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D Operating Voltage Range of 4.5 V to 5.5 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 12 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max D Inputs Are TTL-Voltage Compatible SN54HCT377 . . . J OR W PACKAGE SN74HCT377 . . . DW OR N PACKAGE (TOP VIEW) SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 D Contain Eight Flip-Flops With Single-Rail Outputs D Clock Enable Latched to Avoid False Clocking D Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators SN54HCT377 . . . FK PACKAGE (TOP VIEW) 1D 1Q CLKEN VCC 8Q CLKEN 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK 2D 3 2 1 20 19 4 18 8D 2Q 5 17 7D 3Q 6 16 7Q 3D 7 15 6Q 4D 8 14 6D 9 10 11 12 13 4Q GND CLK 5Q 5D description/ordering information These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273 devices, but feature a latched clock-enable (CLKEN) input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74HCT377N SN74HCT377N –40°C to 85°C SOIC – DW Tube Tape and reel SN74HCT377DW SN74HCT377DWR HCT377 CDIP – J Tube SNJ54HCT377J SNJ54HCT377J –55°C to 125°C CFP – W Tube SNJ54HCT377W SNJ54HCT377W LCCC – FK Tube SNJ54HCT377FK SNJ54HCT377FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2003, Texas Instruments Incorporated 1 SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 FUNCTION TABLE (each flip-flop) INPUTS CLKEN CLK D OUTPUT Q H X X Q0 L ↑ H H L ↑ L L X L X Q0 logic diagram (positive logic) CLKEN 1 CLK 11 3 1D 4 2D 7 3D 8 4D 13 5D 14 6D 17 7D 18 8D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D C1 1D 2 1Q 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and out.


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