BUS TRANSCEIVERS-REGISTERS. SN54HCT646 Datasheet

SN54HCT646 TRANSCEIVERS-REGISTERS. Datasheet pdf. Equivalent


Part SN54HCT646
Description OCTAL BUS TRANSCEIVERS-REGISTERS
Feature D Operating Voltage Range of 4.5 V to 5.5 V D Low Power Consumption, 80-µA Max ICC D Typical tpd = 1.
Manufacture etcTI
Datasheet
Download SN54HCT646 Datasheet


D Operating Voltage Range of 4.5 V to 5.5 V D Low Power Cons SN54HCT646 Datasheet
Recommendation Recommendation Datasheet SN54HCT646 Datasheet




SN54HCT646
D Operating Voltage Range of 4.5 V to 5.5 V
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 12 ns
D ±6-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Inputs Are TTL-Voltage Compatible
SN54HCT646 . . . JT OR W PACKAGE
SN74HCT646 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
D Independent Registers for A and B Buses
D Multiplexed Real-Time and Stored Data
D True Data Paths
D High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
SN54HCT646 . . . FK PACKAGE
(TOP VIEW)
CLKAB 1
SAB 2
DIR 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
A8 11
GND 12
24 VCC
23 CLKBA
22 SBA
21 OE
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 B8
4 3 2 1 28 27 26
A1 5
25 OE
A2 6
24 B1
A3 7
23 B2
NC 8
22 NC
A4 9
21 B3
A5 10
20 B4
A6 1112 13 14 15 16 17 1819 B5
description/ordering information
NC – No internal connection
The ’HCT646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’HCT646 devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – NT
Tube
SN74HCT646NT
SN74HCT646NT
–40°C to 85°C
SOIC – DW
Tube
Tape and reel
SN74HCT646DW
SN74HCT646DWR
HCT646
CDIP – JT
Tube
SNJ54HCT646JT
SNJ54HCT646JT
–55°C to 125°C CFP – W
Tube
SNJ54HCT646W
SNJ54HCT646W
LCCC – FK
Tube
SNJ54HCT646FK
SNJ54HCT646FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
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SN54HCT646
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C MARCH 1984 REVISED MARCH 2003
description/ordering information (continued)
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and /or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR CLKAB CLKBA SAB SBA
A1A8
B1B8
X
X
X
X
X
Input
Unspecified
X
X
X
X
X
Unspecified
Input
OPERATION OR FUNCTION
Store A, B unspecified
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B data
H
X
H or L H or L
X
X
Input disabled Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265







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