M-LVDS Transceiver. DS91D176 Datasheet

DS91D176 Transceiver. Datasheet pdf. Equivalent


Part DS91D176
Description 100 MHz Single Channel M-LVDS Transceiver
Feature DS91C176, DS91D176 www.ti.com SNLS146L – MARCH 2006 – REVISED APRIL 2013 DS91D176/DS91C176 100 MH.
Manufacture etcTI
Datasheet
Download DS91D176 Datasheet


DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers Feb DS91D176 Datasheet
DS91C176, DS91D176 www.ti.com SNLS146L – MARCH 2006 – REVI DS91D176 Datasheet
Recommendation Recommendation Datasheet DS91D176 Datasheet




DS91D176
DS91C176, DS91D176
www.ti.com
SNLS146L – MARCH 2006 – REVISED APRIL 2013
DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers
Check for Samples: DS91C176, DS91D176
FEATURES
1
2 DC to 100+ MHz / 200+ Mbps Low Power, Low
EMI Operation
• Optimal for ATCA, uTCA Clock Distribution
Networks
• Meets or Exceeds TIA/EIA-899 M-LVDS
Standard
• Wide Input Common Mode Voltage for
Increased Noise Immunity
• DS91D176 has Type 1 Receiver Input
• DS91C176 has Type 2 Receiver with Fail-safe
• Industrial Temperature Range
• Space Saving SOIC-8 Package
DESCRIPTION
The DS91C176 and DS91D176 are 100 MHz single
channel M-LVDS (Multipoint Low Voltage Differential
Signaling) transceivers designed for applications that
utilize multipoint networks (e.g. clock distribution in
ATCA and uTCA based systems). M-LVDS is a new
bus interface standard (TIA/EIA-899) optimized for
multidrop networks. Controlled edge rates, tight input
receiver thresholds and increased drive strength are
sone of the key enhancements that make M-LVDS
devices an ideal choice for distributing signals via
multipoint networks.
The DS91C176/DS91D176 are half-duplex
transceivers that accept LVTTL/LVCMOS signals at
the driver inputs and convert them to differential M-
LVDS signals. The receiver inputs accept low voltage
differential signals (LVDS, B-LVDS, M-LVDS, LV-
PECL and CML) and convert them to 3V LVCMOS
signals. The DS91D176 has a M-LVDS type 1
receiver input with no offset. The DS91C176 has an
M-LVDS type 2 receiver which enable failsafe
functionality.
Typical Application in an ATCA Clock Distribution Network
Slot Card N
Slot Card N+1
MLVDS Transceivers
MLVDS Transceivers
80: RT
80: RT
80: RT
80: RT
80: RT
80: RT
CLK1A (8 KHz)
CLK1B (8 KHz)
CLK2A (19.44 MHz)
CLK2B (19.44 MHz)
CLK3A (User Defined up to 100 MHz)
CLK3B (User Defined up to 100 MHz)
ATCA Backplane
Figure 1. System Diagram
80: RT
80: RT
80: RT
80: RT
80: RT
80: RT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated



DS91D176
DS91C176, DS91D176
SNLS146L – MARCH 2006 – REVISED APRIL 2013
Connection and Logic Diagram
Top View
www.ti.com
Figure 2. SOIC Package
See Package Number D0008A
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Type 1
Type 2
2.4 V
High
xxxxxxxx VID
High
150 mV
50 mV
0V
-50 mV
Low
Low
-2.4 V
Transition Region
Figure 3. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Copyright © 2006–2013, Texas Instruments Incorporated
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